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| ? 6024 silver creek valley road, san jose, california 95138 telephone: (800) 345-7015 ? (408) 284-8200 ? fax: (408) 284-2775 printed in u.s.a. ?2011 integrated device technology, inc. idt ? 89HPEB383 pci express ? bridge user manual july 2011
general disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best possible product. id t does not assume any responsibility for us e of any circuitry described other than t he circuitry embodied in an idt product. the company makes no representations that circuitry described herein is free from pat ent infringement or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of integrated device technology, inc. code disclaimer code examples provided by idt are for illustrative purposes on ly and should not be relied upon for developing applications. any use of the code examples below is completely at your own risk. idt makes no representations or warranties of any kind concerning the noninfringement, quality, safety or su itability of the code, either express or implied, including without limi tation any implied warranties of merchantability, fitness for a p articu- lar purpose, or non-infringement. further, idt makes no represen tations or warranties as to the truth, accuracy or completeness of any statements, information or materials concerning code exam ples contained in any idt publication or public disclosure or that is contained on any idt internet site. in no event will idt be liable for any direct, consequential, incidental, indirect, punitive or special damages, however they may arise, and even if idt has been previously advised about the possibility of such damages. th e code examples also may be subject to united stat es export control laws and may be subject to the export or import laws of other coun tries and it is your res ponsibility to comply with any applicable laws or regulations. life support policy integrated device technology's products are not authorized for us e as critical components in life support devices or systems un less a specific written agreement pertaining to such intended use is executed between t he manufacturer and an officer of idt. 1. life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instru ctions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose failure to per form can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness. idt, the idt logo, and integrated device technology are trademarks or registered trademarks of int egrated device technology, in c. peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required i contents about this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 document conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.1 general features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.2 pcie features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.3 pci features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 pcie interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 eeprom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 power-up signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3. data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.1 upstream data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 downstream data path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 transaction management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 upstream transaction management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.2 downstream transaction management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 upstream non-posted buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.2 upstream posted buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3 downstream non-posted buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.4 downstream posted buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 prefetching algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 short term caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7 polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4. addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 memory-mapped i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 contents ii peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4.3 prefetchable space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5 vga addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 isa addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.7 non-transparent addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7.1 pcie to pci non-prefetchable address remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7.2 pcie to pci prefetchable address remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7.3 pci to pcie address remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8 legacy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5. configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2.1 type 0 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.2 type 1 configuration transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.3 type 1 to type 0 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2.4 type 1 to type 1 forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2.5 type 1 to special cycle forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3 pcie enhanced configuration mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4 configuration retry mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6. bridging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 flow control advertisements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 buffer size and management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4 assignment of requestor id and tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.5 forwarding of pcie to pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.5.1 pcie memory write request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.5.2 pcie non-posted requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.6 forwarding of pci to pcie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.6.1 pci memory write request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.6.2 pci non-posted requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.7 pci transaction support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.8 pcie transaction support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.9 message transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.1 intx interrupt signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.3 locked transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.4 slot power limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.9.5 vendor-defined and device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.10 transaction ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.11 exclusive access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7. pci arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required contents iii 7.3 pci arbitration scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8. interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.3 interrupt routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9. error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.2 pcie as originating interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.2.1 received poisoned tlps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.2.2 received ecrc errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.2.3 pci uncorrectable data errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.2.4 pci uncorrectable address/attribute errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.2.5 received master-abort on pci interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.2.6 received target-abort on pci interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.3 pci as originating interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.3.1 received pci errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.3.2 unsupported request completion status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.3 completer abort completion status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.4 timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.4.1 pcie completion timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.4.2 pci delayed transaction timeout errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.5 other errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.6 error handling tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10. reset and clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.1.1 pcie link reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.1.2 pci bus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.2 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.2.1 pcie clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.2.2 pci clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.1.2 unsupported features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2 power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.1 aspm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.2 l0 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.3 l0s state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.4 l1 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.5 l2/l3 ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.6 l3 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 contents iv peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.3.7 ldn state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.3.8 link state summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3.9 device power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3.10 d0 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3.11 d3 hot state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3.12 d3 cold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.3.13 d state transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.3.14 power management event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.3.15 power state summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12. serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.2 system diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3 eeprom image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.4 functional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.2 tap controller initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.3 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.4 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.5 jtag device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.6 jtag register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 13.6.1 register access from jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 13.6.2 write access to registers from the jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 13.6.3 read access to registers from jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.7 dedicated test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.8 accessing serdes tap controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.2 pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 14.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 14.3.1 pci identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 14.3.2 pci control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14.3.3 pci class register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.3.4 pci miscellaneous 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 14.3.5 pci bus number register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.3.6 pci secondary status and i/o limit and base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.3.7 pci memory base and limit register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 14.3.8 pci pfm base and limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.3.9 pci pfm base upper 32 address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.3.10 pci pfm limit upper 32 address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.3.11 pci i/o address upper 16 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 14.3.12 pci capability pointer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required contents v 14.3.13 pci bridge control and interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14.3.14 secondary retry count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.3.15 pci miscellaneous control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.3.16 pci miscellaneous clock straps register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.3.17 upstream posted write threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.3.18 completion timeout register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.3.19 clock out enable function and debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.3.20 serrdis_opqen_dtc register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4 upstream non-transparent address remapping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.4.1 ntma control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.4.2 ntma primary upper base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.4.3 ntma secondary lower base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.4.4 ntma secondary upper base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.4.5 ntma secondary lower limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.4.6 ntma secondary upper limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5 pci capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5.1 ssid/ssvid capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5.2 ssid capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.5.3 ssid id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.5.4 pci power management capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.5.5 pci power management control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.5.6 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.5.7 secondary bus device mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.5.8 short-term caching period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.5.9 retry timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.5.10 prefetch control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.6 pcie capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.6.1 pcie capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.6.2 pcie device capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.6.3 pcie device control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.6.4 pcie link capabilities register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.6.5 pcie link control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.7 downstream non-transparent address remapping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 14.7.1 secondary bus non-prefetchable address remap control register. . . . . . . . . . . . . . . . . . . . . . . . . . 184 14.7.2 secondary bus non-prefetchable upper base address remap register . . . . . . . . . . . . . . . . . . . . . . 185 14.7.3 secondary bus prefetchable address remap control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 14.7.4 secondary bus prefetchable upper base address remap register . . . . . . . . . . . . . . . . . . . . . . . . . . 186 14.7.5 primary bus non-prefetchable upper base address remap register . . . . . . . . . . . . . . . . . . . . . . . . 186 14.7.6 primary bus non-prefetchable upper limit remap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 14.8 advanced error reporting capability regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 14.8.1 pcie advanced error reporting capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 14.8.2 pcie uncorrectable error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14.8.3 pcie uncorrectable error mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 14.8.4 pcie uncorrectable error severity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.8.5 pcie correctable error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 contents vi peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.6 pcie correctable error mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 14.8.7 pcie advanced error capabilities and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.8.8 pcie header log 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.8.9 pcie header log 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 14.8.10 pcie header log 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.8.11 pcie header log 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 14.8.12 pcie secondary uncorrectable error status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.8.13 pcie secondary uncorrectable error mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.8.14 pcie secondary uncorrectable error severity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.8.15 pcie secondary error capabilities and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.8.16 pcie secondary header log 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.8.17 pcie secondary header log 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.8.18 pcie secondary header log 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.8.19 pcie secondary header log 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 14.8.20 replay latency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 14.8.21 ack/nack update latency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 14.8.22 n_fts register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.9 pcie and serdes control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.9.1 base offset address calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.9.2 pcie per-lane transmit and receive registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.9.3 pcie transmit and receive status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 14.9.4 pcie output status and transmit over ride register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.9.5 pcie receive and output override register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 14.9.6 pcie debug and pattern generator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.9.7 pcie pattern matcher control and error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 14.9.8 pcie ss phase and error counter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14.9.9 pcie scope control and frequency integrator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 14.9.10 pcie clock module control and status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 14.9.11 pcie control and level status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 14.9.12 pcie control and level override register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 15.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 15.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.3 power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 15.4 power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.5 dc operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 15.6 ac timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.6.1 pci interface ac signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 15.6.2 pcie differential transmitter output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 15.6.3 pcie differential receiver input spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 15.6.4 reference clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 15.6.5 boundary scan test signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.6.6 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 15.7 ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required contents vii 16. packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 16.1 pinouts and mechanical diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.1.1 qfp package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.1.2 qfp package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.1.3 qfn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.1.4 qfn package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.3 moisture sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii contents viii peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ix figures figure 1: peb383 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2: peb383 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3: network interface card application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4: dvr card application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5: motherboard application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6: expresscard application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7: upstream data path[update for peb383] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8: downstream data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9: memory-mapped i/o address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10: 64-bit prefetchable memory address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11: i/o address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 12: isa mode i/o addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13: memory window remapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14: pcie configuration address format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15: pci type 0 configuration address format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16: pci type 1 configuration address format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17: pci arbiter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 18: pci arbitration priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 19: arbitration pointers ? example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 20: arbitration pointers ? example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 21: interrupt handling diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 22: pcie flowchart of device error signaling and logging operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 23: transaction error forwarding with pcie as originating interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 24: transaction error forwarding with pci as originating in terface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 25: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 26: pcie clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 27: pci clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 28: pcie link power management states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 29: d state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 30: eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 31: 9-bit eeprom read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 32: 16-bit eeprom read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 33: 9-bit eeprom write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 34: 16-bit eeprom write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 35: eeprom wren instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 36: eeprom rdsr instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 37: read/write access from jtag ? serial data in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 38: observe from jtag ? serial data out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 39: pcie serdes connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 40: transmitter eye voltage and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 41: minimum receiver eye timing and voltage compliance speci fication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 42: weighing function for rms phase jitter calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 figures x peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 43: input timing measurement waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 figure 44: output timing measurement waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 45: pci tov (max) rising edge ac test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 46: pci tov (max) falling edge ac test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 47: pci tov (min) ac test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required xi tables table 1: pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2: pcie interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3: pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4: eeprom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5: jtag interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6: power-up signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7: power supply signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8: completion buffer allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9: initial credit advertisement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10: pci transaction support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 11: pcie transaction support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 12: transaction ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 13: error forwarding requirements (step a to step b) for r eceived pcie errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 14: bridge requirements for transactions requiring a completion (immediate response) . . . . . . . . . . . . . . . . . . . . 68 table 15: error forwarding requirements for received pci errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 16: error forwarding requirements for pci delayed transacti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 17: ecrc errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 18: poisoned tlp errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 19: malformed tlp errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 20: link and flow control errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 21: uncorrectable data/address errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 22: received master/target abort error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 24: request errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 23: completion errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 25: reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 26: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 27: pci clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 28: pcie link states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 29: power management state summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 30: power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 31: eeprom image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 32: pci type 1 configuration header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 33: ssid capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 34: power management capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 35: pcie capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 36: advanced error reporting capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 37: register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 38: serdes per-lane and clock control and status register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 39: tx_lvl values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 40: absolute maximum ratings ? pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 41: absolute maximum ratings ? pcie. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 42: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 tables xii peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 43: peb383 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 44: peb383 power dissipation per supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 45: dc operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 46: pci clock (pci_clk) specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 47: pcie differential transmitter output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 48: pcie differential receiver input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 49: reference clock (pcie_refclk_n/p) electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 50: boundary scan test signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 51: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 52: thermal specifications ? 66mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 53: thermal specifications ? 33mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 1 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required about this document this section discusses the following topics: ? ?scope? on page 1 ? ?document conven tions? on page 1 scope the peb383 user manual discusses the features, configuration requ irements, and design architecture of the peb383. document conventions this document uses th e following conventions. non-differential signal notation non-differential signals are either ac tive-low or active-high. an active-l ow signal has an active state of logic 0 (or the lower voltage level) , and is denoted by a lowercase ?n?. an active-high signal has an active state of logic 1 (o r the higher voltage level), and is not denoted by a special character. the following table illustrates the non-di fferential signal naming convention. differential signal notation differential signals consist of pairs of complement positive and negati ve signals that are measured at the same time to determine a signal?s active or inactive state (they are denoted by ?_p? and ?_n?, respectively). the following table illustrate s the differential signal naming convention. state single-line signal multi-line signal active low namen namen[3] active high name name[3] state single-line signal multi-line signal inactive name_p = 0 name_n = 1 name_p[3] = 0 name_n[3] = 1 active name_p = 1 name_n = 0 name_p[3] is 1 name_n[3] is 0 about this document 2 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required object size notation ?a byte is an 8-bit object. ?a word is a 16-bit object. ?a doubleword (dword) is a 32-bit object. numeric notation ? hexadecimal numbers are denoted by the prefix 0x (for example, 0x04). ? binary numbers are denoted by the prefix 0b (for example, 0b010). ? registers that have multiple iterations ar e denoted by {x..y} in their names; where x is first register and address, and y is the last register and address. for example, reg{0..1} in dicates there are two versions of the register at diff erent addresses: reg0 and reg1. symbols specification status ? version 0.25 ? this specification describes early design and functional information about a device. it is available at the g2 gate, which precedes the defini tion and plan ning phase. ? version 0.5 ? this specification describes early design and functional information about a device. it is available after the g2 gate, but dur ing the definition and planning phase. ? version 0.75 ? this specification describes the ma jority of functional information about a device. it is available at the g3 gate, whic h precedes the development phase. ? version 1.0 ? this specification describes all the functional information about a device. it is available at the g4 gate, which precede s the qualification (t ape-out) phase. tip this symbol indicates a basic design conc ept or information considered helpful. this symbol indicates important conf iguration informatio n or suggestions. this symbol indicates procedures or operating levels that may re sult in misuse or damage to the device. about this document 3 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required revision history october 22, 2009: initial publication of peb383 user manual. november 18, 2009: updated pinouts for qfn and qfp packages. december 8, 2009: updated pinouts and package drawings for qfn and qfp packages. december 18, 2009: added simulated power numbers to tabl e 43. updated tables 51 and 52 with simulated thermal characteristics values. update d pinouts and package drawings for qfn and qfp packages. january 20, 2010: in table 7, changed power numbers for co re, pcie, and pll from 1.0v to 1.05v in the description column and from 1.2v to 1.05v in the design rec. column. in table 42, changed power numbers for core, pcie, and pll from 1. 2v to 1.05v and also changed minimum and maximum values for these 3 parameters. in table 43, changed power numbers for core, pcie, and pll from 1.0v to 1.05v. march 29, 2010: in table 3, changed pull-up re sistor values from 2.4k to 8.2k for interrupts a, b, c, and d. may 5, 2010: in table 42, changed ta min and max temperat ures to 0 and 70 respectively. in section 15.3, updated old table 43 and added new table 44 for power dissipation values. may 28, 2010: in chapter 16, packaging, updated qfp package drawing. added new chapter 17, ordering information. august 3, 2010: in chapter 17, added tape and reel to ordering codes. november 23, 2010: in chapter 16, replaced existing qf n package drawing with revised psc-4327. january 5, 2011: in chapter 13, section 13.7, deleted last bullet containing reference to test_bidir_ctrl. march 7, 2011: in chapter 14, changes bit types labeled re to rwl, added description for rwl in section 14.1, revised descrip tion for bits 0 and 1 in regi ster clkout_enb_func_dbg, and changed reset value in rid field to 0x01 in register pci_clss. in chapter 16, section 16.1.2, added revised 128-pin qfp package drawing. may 17, 2011: in chapter 14, section 14.5.1, added text to the third para graph that starts with ?note that...?. added zb silicon to order page in chapter 17. may 26, 2011: in chapter 15, table 42, changed ma ximum ambient temperature from 70 to 85 o c. june 21, 2011: in chapter 2, table 3, changed pull-up for pci_inta-d pins from 8.2k to 2.4k. july 25, 2011: in chapter 2, table 3, revised text in design recommendation for pcie_refclk pins. about this document 4 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 5 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 1. functional overview topics discussed include the following: ? ?overview? ? ?features? ? ?device architecture? ? ?typical applications? 1.1 overview the idt peb383 is a high-performan ce bus bridge that connects the pci express (pcie) protocol to the pci bus standard (see figure 1 ). the peb383?s pcie interface supports a x1 lane pcie configuration. this enables the bridge to offer exceptional throughput performance of up to 2.5 g bps per transmit and receiv e direction. the device?s pci interface can operate up to 66 mhz. this inte rface offers designers extensive flexibility by supporting the flowing addr essing modes: transparent, and non-transparent. 1. functional overview > features 6 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 1: peb383 block diagram 1.2 features the peb383?s key features are liste d in the following sub-sections. 1.2.1 general features ? forward bridge, pcie to pci ? single store and forward fo r optimal latency performance ? supports two modes of addressing: ? transparent: for efficient, flow-through configurations ? non-transparent: for addr ess remapping of the pcie and the pci domains ? compliant to the following specifications: ? pci express base specification (revision 1.1) ? pci express-to-pci/pci-x bridge specification (revision 1.0) ? pci-to-pci bridge specification (revision 1.2) ? pci local bus specification (revision 3.0) ? pci bus power management interf ace specification (revision 1.2) 1. functional overview > features 7 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? 3.3v pci i/os with 5v tolerant i/os ? support for four external pci bus ma sters through an integrated arbiter ? support for external pci bus arbiter ? support for masquerade mode (can ov erwrite vendor and device id from eeprom) ? jtag ieee 1149.1, 1149.6 ? support for d0, d3 hot, d3 cold power management states ? support for subsystem id (ssid) and subsystem vendor id (ssvid) ? legacy mode support for subtractive decode ? exclusive access using pci_lockn ? packaged in a 14x14mm 128 pin tqfp and a 10x10mm 132 pin qfn. 1.2.2 pcie features ? 1 lane ? 128-byte maximum payload ? advanced error reporting capability ? end-to-end crc (ecrc) check and generation ? up to four outstanding memory reads ? 512-byte read completion buffer ? aspm l0s link state power management ?aspm l1 ? legacy interrupt signaling 1.2.3 pci features ? 32/64-bit addressing ? 32-bit data bus ?5v tolerant ? exclusive access using pci_lockn ? 25-, 33-, 50-, and 66-mhz operation ? up to four outstanding read requests ? 1-kb read completion buffer ? clock outputs for four pci devices ? short-term caching support 1. functional overview > device architecture 8 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 1.3 device architecture a high-level, architectur al diagram of the peb383 is displayed in figure 2 . for more information about data flow through the device, see ?upstream data path? and ?downstream data path? . figure 2: peb383 device architecture packets received on the pcie interface are processed by the data link layer and transaction layer, if applicable. if a packet is destined for the transaction layer, its addre ss is decoded and forwarded to the appropriate destination: ? configuration register ? downstream posted write buffer ? downstream read request queue ? downstream read completion buffer rx ph y serd es con figur atio n reg ister s data link layer 1k replay buffers pc ie (pri mary in terface) pci interface (secondary interface) target interface 5 1 2 ( 4 e n t r y ) u p s t r e a m p o s t e d w r i t e b u f f e r s ma st er i n te rf ac e tr an sa ct ion la ye r tx phy ser des data link layer transaction layer ordering or de ri ng ad dr es s de co d i ng pci ar bit er jtag eeprom cl k/ re se t 8 e n t r y u p s t r e a m r e a d r e q u e s t q u e u e read st ate cac h e 5 1 2 b y t e ( 8 e n t r y ) d o w n s t r e a m p o s t e d w r i t e b u f f e r s 5 1 2 b y t e ( 4 e n t r y ) d o w n s t r e a m r e a d c o m p l e t i o n b u f f e r 4 e n t r y d o w n s t r e a m r e a d r e q u e s t q u e u e read st ate cache address decoding flow control ac k/n oac k config writes & read request co nf i g r ea ds 1 k ( 8 e n t r y ) u p s t r e a m r e a d c o m p l e t i o n b u f f e r 1. functional overview > device architecture 9 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required pci data that is destined for the pc ie fabric are subject to pcie orderi ng rules. data is pulled from the appropriate queue: ? configuration register ? upstream posted write buffer ? upstream read request queue ? upstream read completion buffer pci transactions that are decoded for the pcie a ddress space are forwarded to the appropriate queue: ? upstream read request queue ? upstream posted write buffer transactions destined for downstream devices on the pci bus, are subject to pci ordering rules. data is pulled form the appropriate queue: ? downstream posted write buffer ? downstream read request queue pcie is a serialized protocol at th e physical layer, and a packetized pr otocol at the data link layer. the pcie lane operates at 2.5 gb symbol rate, or at 2.0 g b data rate; the difference is a result of the 8/10b coding process. the peb383 uses the following proces ses to ensure the accurate and timely delivery of data through the data link layer: ? credit-based flow control ? prev ents data loss and congestion ? ack/noack protocol and end-to-end crc (ecrc) ? en sures reliable data delivery if bit errors occur ? replay buffer ? replays packets that ar e not acknowledged by the receiver (nak) in contrast, pci is a para llel data interface at the physical laye r. pci is a non-packetized protocol. when a bus master starts a read or a write transactio n, it indicates only the st arting transaction address to the target, and not the size of the read or write. in the case of a pci write, which is initiated on the pci interface and is destined for th e root complex, the data is writt en into an upstream posted write buffer in the peb383. the end of the write transact ion is signaled by the master on the pci bus. once the write is completed the data can be forwarded to the pcie interface. if the posted write buffer is about to overflow, the peb383 in dicates a retry/disconnect on th e pci bus. once the posted write buffer empties, the peb383 can accept additional write transactions. the pe b383 will split write transactions as required to meet pcie constraints: to prevent a writ e crossing a 4-kb bo undary; if byte enables are used throughout the transaction; or if the quantity of data exceeds the maximum payload size (see max_size in ?pcie device capa bilities register? ). the upstream posted write buffer is managed as a simple fifo. 1. functional overview > typical applications 10 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required a read initiated on the pci bus that is decoded for an upstream target is handled as a delayed transaction by the peb383. the bridge latches the read transaction and attempts to reserve buffer space in its upstream read completion buffer. if space is successfully reserved in the buffer, the peb383 initiates a read on the pcie interface. when the read da ta is returned from the root complex, it is stored in the upstream read completion buffer. pci-initiated reads, however, do not de fine the amount of data to read. once the master on the pci bus retries the read transaction, the tr ansaction is checked to determine if the read data is returned. if it has th e read data, the peb383 responds as the target and transfers the read data to the pci bus. note the ups tream read completion buffer is not a simple fifo, as the order that masters on the pci bus retry is not deterministic. if the completion buffer becomes empty prior to the transaction completing, the pe b383 disconnects from the pci bus. when the read transaction is completed, the peb 383 discards any prefetched data that is not used and frees up the buffer. the maximum number of outsta nding read requests per master is controlled by dtl[7:0] bits in ?secondary retry count register? . a write initiated on the pcie interface with the target on the downstream pci bus is written into the downstream posted write buffer. th e peb383 acts as the master for th e transaction and arbitrates for the pci bus and initiates the write transaction. th e downstream posted write buffer is managed as a fifo. there will always be space av ailable in the buffer to accept p acket data because of the flow control method used by the pcie data link layer. if the downstream posted write buffer is about to overflow, the upstream device will be informed of this by its lack of credits and will not send any more write data to the peb383. a read initiated on the pcie interface with the target on the downstream pci bus is written into the downstream read request queue. the downstream read request queue is mana ged with flow control credits to prevent overflowing. the peb383 latches th e read transaction and at tempts to reserve space in the downstream read co mpletion buffer. if space is successfully reserved in the buffer, the peb383 acts as the master for the trans action and initiates a read transaction on the pci bus.programmable address decoders instruct the pe b383 which transactions on the pc i bus to forward upstream, and which transactions on the pcie link to forward downstream. 1.4 typical applications this section illustrates some typical applications for the peb383. figure 3: network interface card application 80e2000_ta001_01 32-bit, 66-mhz pci x1 pcie peb383 integrated cpu fe usb gbe 1. functional overview > typical applications 11 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 4: dvr card application figure 5: motherboard application 80e2000_ta002_01 pci bus x1 pcie peb383 camera video decoder camera video decoder camera video decoder camera video decoder 80e2040_ta001_01 pci 10x10 mm footprint supports up to four pci devices off x1 pcie pcie peb383 pci slot pci slot processor chipset cpu pcie slot peripherals graphics memory 1. functional overview > typical applications 12 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 6: expresscard application 80e2010_ta001_01 x1 pcie peb383 pci i/o controller 13 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2. signal descriptions topics discussed include the following: ? ?overview? ? ?pcie interface signals? ? ?pci interface signals? ? ?eeprom interface signals? ? ?jtag interface signals? ? ?power-up signals? ? ?power supply signals? 2.1 overview signals are classified acco rding to the types defined in the following table. table 1: pin types pin type definition 3.3 od 3.3v cmos open-drain output 3.3 3-state 3.3v cmos tri-state output 3.3 bidir 3.3v cmos bi-directional 3.3 bidir pu 3.3v cmos bi-directional with 265k (+/- 45k) pull-up resistor 3.3 bidir od 3.3v cmos bi-directional open-drain 3.3 in 3.3v cmos input 3.3 in pu 3.3v cmos input with 265k (+/- 45k) pull-up resistor 3.3 out 3.3v cmos output pci bidir pci bi-directional pci bidir od pci bi-directional open-drain pci in pci input pci out pci output pci od pci output open-drain 2. signal descriptions > pcie interface signals 14 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2.2 pcie interface signals pcie diff out pcie differential output pcie diff in pcie differential input table 2: pcie interface signals name pin type description design recommendation pcie_perstn 3.3 in master reset in: 0 = peb383 in reset 1 = peb383 in normal mode direct connect to the perst# signal. pcie_txd_n pcie_txd_p pcie diff out transmit data. these differential pair signals send pcie 8b/10b encoded symbols and an embedded clock to the link partner. dc blocking capacitors must be placed in the link between the transmitter and the receiver. place a 0603 or 0402 0.075uf to 0.1uf ceramic capacitor on each txd_n, txd_p signal. pcie_rxd_n pcie_rxd_p pcie diff in receive data. these differential pair signals receive pcie 8b/10b encoded symbols and an embedded clock from the link partner. dc blocking capacitors must be placed in the link between the transmitter and the receiver; however, the dc blocking capacitors are normally placed near the transmitter. when designing an add-in card, capacitors are not required on this link. when designing a system board, the dc blocking capacitors should be placed near the transmitter. pcie_refclk_n pcie_refclk_p pcie diff in reference clock. 100-mhz differential reference clock. refer to board design guidelines. pcie_rext analog - this signal must be connected to vss with a 191-ohm (1%) resistor. table 1: pin types (continued) pin type definition 2. signal descriptions > pci interface signals 15 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2.3 pci interface signals table 3: pci interface signals name pin type description design recommendation pci_ad[31:0] pci bidir address/data bus. these multiplexed signals provide a 32/64-bit address and 32-bit data bus. none. pci_cben[3:0] pci bidir command/byte enables. these multiplexed signals indicate the current transaction type. none. pci_clk pci in pci input clock. this signal provides timing for the peb383, either from an external clock or from one of the pci_clko[4:0] signals (see ?clocking? ). none. pci_clko[4:0] pci out pci output clocks (see ?clocking? ). point-to-point connection to pci device. idt recommends a 33 ohm series termination resistor. in master clocking mode, pci_clko[4] should be connected to pci_clk. pci_devseln pci bidir device select. a target device asserts this signal when it decodes its address on the bus. the master samples the signal at the beginning of a transaction, and the target rescinds it at the end of the transaction. pull up (8.2k) to vio_pci. pci_framen pci bidir frame. the current initiator drives this signal to indicate the start and duration of a transaction, and the bus target samples it. the bus master rescinds the signal at the end of the transaction. pull up (8.2k) to vio_pci. 2. signal descriptions > pci interface signals 16 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required pci_gntn[3:0] pci bidir / pci out bus grant. the peb383 uses these multifunction signals to grant access to the pci bus; however, they are used differently depending on whether or not the peb383 pci arbiter is used. if the arbiter is used, then pci_gntn[3:0] are outputs used by the peb383 to grant access to the bus (see ?pci arbitration? ). if an external arbiter is used, pci_gntn[0] is an input that is driven by the arbiter to grant the peb383 access to the bus. the remaining pins, pci_gntn[3:1], remain as outputs. the input/output mode is controlled by bit[9] of ?pci miscellaneous 0 register? on page 129 . note: the pci bus arbiter can be placed on the last bus master by bit[8] of ?pci miscellaneous 0 register? on page 129 . pci_gntn[3:0] outputs connect directly to the pci device?s pci_gntn inputs. pull ups are not required on unused outputs. pci_intdn pci in interrupt d. pull-up (2.4k) to vio_pci. pci_intcn pci in interrupt c. pull-up (2.4k) to vio_pci. pci_intbn pci in interrupt b. pull-up (2.4k) to vio_pci. pci_intan pci in interrupt a. pull-up (2.4k) to vio_pci. pci_irdyn pci bidir initiator ready. the bus master asserts this signal to indicate it is ready to complete the current transaction. pull-up (8.2k) to vio_pci. pci_lockn pci od lock. this signal is used by the bus master to lock the currently addressed memory target during a series of exclusive access transactions (see ?exclusive access? ). pull up (8.2k) to vio_pci. table 3: pci interface signals (continued) name pin type description design recommendation 2. signal descriptions > pci interface signals 17 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required pci_m66en pci in 66-mhz enable. this signal enables the pci interface for 66-mhz operation. 0 = 33-mhz operation 1 = 66-mhz operation pci_m66en is used only in master clocking mode. embedded designs tied to ground for 33-mhz operation; otherwise, pull up to vio_pci. bused designs using pci slots for add- in cards place a 10k pull-up resistor (to vio_pci) on pci_m66en and route the signal from slot to slot. in slave clocking mode, pci_m66en can be tied to ground. pci_par pci bidir parity. this signal carries even parity across pci_ad[31:0] and pci_cben[3:0]. the bus master asserts this signal for the address and write data phases. the bus target asserts it for read data phases. no pull-up or pull-down resistor is required. pci_perrn pci bidir parity error. this signal indicates a parity error occurred during the current data phase. the bus target that receives the data asserts this signal. pull up (8.2k) to vio_pci. pci_pmen pci in power management event. this signal indicates a power management event occurred (see ?power management? ). pull up (8.2k) to vio_pci. pci_reqn[3:0] pci in pci bidir bus request. these signals are used to request access to the pci bus. they are used differently, however, depending on whether or not the peb383 pci arbiter is used. if the pci arbiter is used, then pci_reqn[3:0] are inputs used by external masters to request access to the bus. if an external arbiter is used, pci_reqn[0] is an output used by the peb383 to request access to the bus, while pci_reqn[3:1] should be pulled high, as they are still inputs. the input/output mode is controlled by bit[9] of ?pci miscellaneous 0 register? on page 129 . note: the pci bus arbiter can be placed on the last bus master by bit[8] of ?pci miscellaneous 0 register? on page 129 . pull up (8.2k) to vio_pci. table 3: pci interface signals (continued) name pin type description design recommendation 2. signal descriptions > eeprom interface signals 18 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2.4 eeprom interface signals pci_rstn pci out pci reset: this signal resets all devices on the pc bus. no pull-up or pull-down resistor is required. pci_serrn pci bidir od system error. this signal indicates an address or attribute phase parity error occurred. pull-up (8.2k) to vio_pci. pci_stopn pci bidir stop. a bus target asserts this signal to indicate it wants to stop the current transaction on the current data phase. pull-up (8.2k) to vio_pci. pci_trdyn pci bidir target ready. the bus target asserts this signal to indicate it is ready to complete the current data phase. pull-up (8.2k) to vio_pci. table 4: eeprom interface signals name pin type description design recommendation sr_clk 3.3 out serial rom clock: this signal is derived from refclkn/p (see ?system diagram? ). no pull-up or pull-down resistor is required. sr_csn 3.3 out serial rom chip select: this active-low signal activates the chip-select (cs) on the external eeprom. sr_din 3.3 out serial rom data in: this signal transfers output data from the peb383 to the eeprom. sr_dout 3.3 in pu serial rom data out: this signal transfers input data from the eeprom to the peb383. table 3: pci interface signals (continued) name pin type description design recommendation 2. signal descriptions > jtag interface signals 19 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2.5 jtag interface signals 2.6 power-up signals table 5: jtag interface signals name pin type description design recommendation jtag_tck 3.3 in test clock. this signal clocks state information and data into and out of the peb383 during boundary scan. connect to 3.3v using a 2k pull-up resistor. jtag_tdi 3.3 in pu test data input. this signal, in conjunction with jtag_tck, shifts data and instructions into the tap controller in a serial bit stream. connect to 3.3v using a 2k pull-up resistor. jtag_tdo 3.3 out test data output. this signal, in conjunction with jtag_tck, shifts data and instructions from the tap controller in a serial bit stream. if jtag is not used, leave unconnected. jtag_tms 3.3 in pu test mode set. this signal controls the state of the tap controller. connect to 3.3v using a 2k pull-up resistor. jtag_trstn 3.3 in pu test reset. this signal forces the tap controller into an initialized state. this signal must be pulsed or pulled low externally to reset the tap controller. if jtag is not used, connect this pin to a 2k pull-down resistor. if jtag is used, connect to output of and gate where inputs are trst# and perst#. for more information, see the peb383 evaluation board user manual . test_bce 3.3 in test boundary scan compatibility enabled. this input aids 1149.6 testing and scope function of phys. for 1149.1 boundary scan testing, this pin must be low. for 1149.6 boundary scan testing, this pin must be high. test_on 3.3 in this signal controls scan shift enable. pull down for normal operation. table 6: power-up signals name pin type description design recommendation pwrup_pll_ bypass 3.3 in pll bypass. this signal bypasses the pll in the pci clock generation (see ?pci clocking? ). 0 = normal operation 1 = pll bypass this signal should always be tied low. 2. signal descriptions > power supply signals 20 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2.7 power supply signals table 7: power supply signals name pin type description design recommendation a a. for filtering and decoupling information for these signals, see ?power supply filtering and decoupling? in the peb383 board design guidelines . vdd core power 1.05v core power none. vdd_pci i/o power 3.3 volt i/o power for pci and 3.3v i/o power for cmos none. vdd_pcie core power 1.05v power for serdes connect these signals to the 1.05v source through a ferrite bead. b b. for more information, see ?analog power supply filtering? in the peb383 board design guidelines . vdda_pcie analog power 3.3v analog power for serdes connect these signals to the 3.3v source through a ferrite bead. b vdda_pll analog power 1.05v analog power for pll connect these signals to the 1.05v source through a ferrite bead. b vio_pci i/o power 5.0 i/o power, for 5.0v i/o compliance. this signal can also be tied to 3.3v if 5.0v compliance is not required. connect these signals to a 3.3v or 5v source depending on the pci devices attached to the peb383 pci bus. vss gnd gnd, core power none. vss_io gnd gnd, i/o power none. vssa_pll gnd gnd, analog pll power none. 21 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 3. data path topics discussed include the following: ? ?overview? ? ?transaction management? ? ?buffer structure? ? ?flow control? ? ?prefetching algorithm? ? ?short term caching? ? ?polarity inversion? 3.1 overview the peb383 uses two buffering methods for tran sferring data between its pcie and pci ports: ? two-stage buffering for its upstream data path ? one-stage buffering in its downstream data path these buffering methods are summari zed in the following sub-sections. 3.1.1 upstream data path two-stage buffering in the upstream path consists of two different sized buffers for each transaction type: posted, no n-posted, and completion (see figure 7 ). the first-stage buffering in the pci core, which supports the store and forward method, meets the synchronization requirements of pc i and pcie. this buffer design al so provides optimized throughput and improved latencies. the second-stage buffering in the pcie core, wh ich supports the cut-thro ugh method, handles the possible backpressure due to scaled down link, lack of flow control credits, and replay. posted and completion buffers allow the peb383 to accept a few more cycles of data transfer even after the assertion of stall which indicates to the initiator in the pci core to stop the data transfer. this buffer design ensures idle cycles are not inserted in data cycles while forwarding tlps to its egress block. 3. data path > overview 22 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 7: upstream data path[update for peb383] 3.1.2 downstream data path in the downstream path, the peb3 83 uses one-stage buffering for each type of transaction (see figure 8 ). these buffers support the store and forwar d method, receive flow control, protocol differences, synchronization, a nd error handling requirements. s c r a m b l e r posted fifo ( 512 bytes) non posted fifo 4 entr ies completion fi fo (64 bytes) retry bu ffer (1 kb ) error message tlp ehu cs r pme_n m a s t e r i n t e r f a c e t a r g e t i n t e r f a c e posted b uffer (512 bytes) non p osted q ueue 8 entr ies do w n s t r e a m re a d completion b uffer (512 byte s) pmc pme mesaage tlp posted request non-pos ted request co m p le t i o n s claim cycle address decoder 2 nd st age b uff eri ng cut through 1 st stage buffering store and forward pc ie c ore pci core device core int e rf a ce 3. data path > transaction management 23 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 8: downstream data path 3.2 transaction management the following sub-sections describe how the peb383 handles upstream and do wnstream transactions. 3.2.1 upstream transaction management transactions that originate on the pc i interface that are dest ined for the pcie interface are stored in the respective queues or buffers in the pci clock domain , and are then forwarded to the pcie core (see figure 7 ). pci buffer logic decomposes the received tr ansactions as per the pcie constraints (for example, max_rd_size, max_pay_size, rcb, and 4- kb address boundary). three sets of data and control signals for the three types of transactions (posted, non-posted, and completions) are used between the pci and pcie cores. transactions are stored temporarily in the pcie core buffers before they are used to construct tlps, and are then made visible to tlp arbiter. the tlps are processed by the tlp arbiter only after ordering rules are satisfied. the tlp arbiter selects one of the five input tlps (error message, pme message, posted, completion, and non-posted tlps) in a round-robi n mode if sufficient credits and retry buffer space is available for the specific tlps. the tlp arbiter continue s to check the available credit and retry buffer space against each of the active inputs, and select s the one that meets the constraint. the ecrc adder calc ulates and appends a 32-bit ecrc value to the end of the tlp selected by the arbiter if ecrc gene ration is enabled by software, an d then forwards the tlp to the data link layer. p c i i n t e r f a c e r x s e r d e s d e - s c r a m b l e r b y t e u n - s t r i p e r lc rc checker pa cke t decoder address decod er ec rc ch e ck e r tlp error de t e ct e r reques t generator a r b i t e r m a s t e r i n t e r f a c e t a r g e t i n t e r f a c e posted buf fer (512 bytes ) non-posted queue 4 entries upstream read completion buffer (1 k b) pcie core pc i co r e receive flow control buffers delayed completion d evi ce co re int erf ace 3. data path > buffer structure 24 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the data link layer applies a se quence number to the tlp received fro m transaction layer block, and then calculates and appends a 32-bit lcrc value to ensure integrity during th e transmission across the physical lanes. a copy of the tlp sent to the physical layer is stored in the retr y buffer for future replay if there is negative acknowledgement from the ot her end component. the retry buffer replays the stored unacknowledged tlps if it recei ves a nak or replay timer expiration. the byte striper block of the physical layer unit appends start and end characters to the tlp received from data link layer, and then multiplexes the byte s of the packet onto the lanes. these bytes on the lanes are scrambled using lfsr to eliminate repetitive bit patterns in the bit stream. the scrambled 8-bit characters are sent to the serdes to convert to a 10-bit character in order to transmit it in a serial bit stream on the physical lanes. 3.2.2 downstream transaction management in the downstream path, the physical layer unit conver ts the incoming serial bit stream into a parallel symbol stream, de-scrambles the by tes in the transmit path, assembles packets, and then sends them to the data link layer unit (see figure 8 ). the data link layer unit checks for lcrc and sequen ce number errors for pack ets received from the physical layer unit. if there are no errors, lcrc and sequence number fields are stripped and resultant tlp is sent to transaction layer unit. the transaction layer unit checks for ecrc errors an d framing violations base d on header fields and ecrc fields in the tlp received from the data link layer unit. it extracts routing information based on the header fields and dete rmines whether to forward or reject th e tlp. the ecrc field is stripped and the resulting information in the tlp header, payload, and any detected e rror information, is sent to the pci core. the peb383 uses receive flow cont rol buffers in the pci core instea d of in the pcie core to store downstream requests or completions to be forwarded on the pci interface. 3.3 buffer structure the following sub-sections describe the three peb383 buffer structures: ? upstream non-posted buffer ? upstream posted buffer ? downstream non-posted buffer ? downstream posted buffer 3.3.1 upstream non-posted buffer there are four entries in the upstream read request queue. the 1-kb completion buffer is split up into 4 x 256-byte segments. when a read o ccurs on the pci bus a read reques t is fifo queued in one of the 4 entry non-posted request queue, if there is space. th e pci transaction is retried so that the master will return when the bridge has fetched the data. if th ere are unallocated completion buffers (equal or greater than the programe d allocation size) a pcie read reques t is sent upstr eam, requesting the programed allocation amount of data. 3. data path > buffer structure 25 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required by default the programed allocation am ount of buffers that are allocated is equal to the prefetch size. in order to prevent one device from consuming all the buffers, the allocation size can be programmed to be less than the prefetch size. for example, if the prefetch size was set to 1 kb, then only one outstanding request would result, as once all the buff ers are allocated no more requests can be sent. the allocation size can be programmed to be 512 bytes (or 2 56, 128) so that 1, 2, or 4 outstanding requests are possible (see max_bu f_aloc bits in the ?upstream posted writ e threshold register? ). the requests are sent in order ? sm all requests do not pass large requests ? as completion buffers are unallocated. otherwise, this would cause unfairness since smaller requ ests could block larger requests. the completions can occur out of order; that is, the bridge always responds with completion data if it is in the buffers. this is done to improve throughput when there are multiple out standing read requests. 3.3.1.1 non-posted write buffer the peb383 supports one non-posted write transac tion. similar to read requests, it s request information is stored in one of the eight request queue entries, and its da ta is stored in a 32-bit register. non-posted write requests are fo rwarded onto the pcie core in two pcie clock cycles. request information is forwarded in the first cycle, while 32-bit data is forwarded in the second cycle. 3.3.2 upstream posted buffer the upstream posted buffer is a fifo of size 512 by tes that stores memory write transactions that originate on the pci interface and ar e destined to devices on pcie interface. the peb383 completes the posted transactions on the originating bus before forwarding them to the pcie interface. unlike the read buffers, the amount of space assigned to each transaction is dyn amic. a single transaction can use 512 bytes of buffer space. the peb3 83 translates all types of memory write transactions from the pci interface to memory write requests on the pcie interface. the peb383 terminates a new transaction with retry and an active transaction with disconn ect if sufficient buffer space is not available. the peb383 uses an 8-deep request fifo to store the request information, including first and last dwords byte enables of the received transactions. table 8: completion buffer allocation bit setting -----> max_buf_aloc 0b11 0b10 0b01 0b11 prefetch aloc a a. completion buffer allocation in bytes. orr b b. number of outstanding read requests. aloc orr aloc orr aloc orr 1024 bytes 1024 1 512 2 256 4 256 4 512 bytes 512 2 512 2 256 4 256 4 256 bytes 256 4 256 4 256 4 256 4 128 bytes 128 4 128 4 128 4 128 4 3. data path > flow control 26 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required memory write transactions can contain any or all invalid payload bytes, where as memory write and invalidate (mwi) transactions carry all the valid pa yload bytes. the peb383 decomposes the received transactions with non-contiguous byte enables on 32-byte boundaries while writing into the request fifo. the pci core makes a request to the pcie core if one of the following conditions is met: ? all data bytes of the transaction are r eceived and are stored in the data buffer ? received data bytes count exceeds the programme d threshold value (see upst_pwr_thres in ?upstream posted writ e threshold register? ) ? received data bytes count exceeds the pcie maximum payload size (see max_pay_size in ?pcie device control an d status register? ) ? address plus received data bytes count exceeds 4 kb ? data with non-contiguous byte enables 3.3.3 downstream non-posted buffer the 512-byte, downstream non-posted buffer stores th e data returned for the non-posted requests that originate on the pcie interface and are destined for pci devices. a single completion of up to 512-bytes can be stored here. a single out standing read is issued to the pci side. 3.3.4 downstream posted buffer the 512-byte downstream posted write buffer stores the payload of memory write transactions that originate on the pcie interface an d are destined for pci devices. th e amount of space assigned to each transaction is dynamic. the peb383 uses an 8-deep request fifo to store the request information, in cluding the first and last dwords byte enables. the peb383 initiates a transa ction on the pci interface only after a complete packet is stored in the buffer. th e peb383 attempts another outstanding transaction only if the current transaction is either su ccessfully completed or te rminated with either ma ster or target abort. 3.4 flow control the peb383 handles packet-based protocol on its pcie interface, and transaction-based protocol on its pci interface. pci requesters initiate transactions without prior knowledge on receiver buffer status. as a result, flow control is mana ged through retries and disconnects that can waste bus bandwidth. in comparison, pcie requesters initiate requests while having prior knowledge on receiver buffer availability status, and therefore, eliminate the wasteful effects of unnecessa ry retries and disconnects. the peb383 does not issue retries or disconnects on the pci interface for comp letions returned for a downstream read request, but may issue retries or disconnects for a posted or non-poste d transaction on the pci interface based on the buffer space availability. 3. data path > pr efetching algorithm 27 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the peb383 uses flow control buffer s in the pci core for three categories of downstream traffic. the amount of flow control buffer space availability is conveye d to the other end of the component using flow control credits. the peb383 a dvertises infinite credits for comple tions as it ensure s enough buffer space is available to store the returned completion data before initiating a read request. the peb383 advertises initial flow control credits as follows. each credit of data is 16 bytes. 3.5 prefetching algorithm the peb383 prefetches the data by default for the tr ansaction that uses memory read line or memory read multiple command. the peb383 does not prefetch the data by default for the transaction that uses the memory read command since the bridge does not know whether or not the transaction address falls in prefetchable region. the prefetch algorithm is configured for various commands as follows: ? memory read ? controlled by p_mr, mrl_66 and mrl_33 of the ?prefetch control register? . the default value of these bits in dicates that either one dword in 32-bit bus mode or two dwords in 64-bit bus mode is prefetched. ? memory read line ? controlled by p_mrl, mrl_66 and mrl_33 of the ?prefetch control register? . the default value of these bi ts indicates that either 128 bytes in 32-bit bus mode or 256 bytes in 64-bit bus mode is prefetched. the peb383 prefetches one cacheline if p_mrl is set to 0. ? prefetch algorithm for memory read multiple command is controlled by p_mrm, mrm_66 and mrm_33 of the ?prefetch control register? . the default value of these bits indicates that either 256 bytes in 32-bit bus mode or 384 bytes in 64-bit bus mode is prefetched. the peb383 prefetches two cachelines if p_mrm is set to 0. table 9: initial credit advertisement credit type initial advertisement posted header (ph) 0x08 posted data (pd) 0x020 non-posted header (nph) 0x04 non-posted data (npd) 0x01 completion header (cplh) 0x00 (infinite) completion data (cpld) 0x000 (infinite) 3. data path > short term caching 28 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 3.6 short term caching this feature provides performance im provements in situations where up stream devices are not able to stream data continuously to meet the prefet ching needs of the peb383. as defined in the pci-to-pci bridge specification (revision 1.2) , when the bus master completes a transaction, the bridge is required to discard the balance of any data that was prefet ched for the master. to prevent performance impacts when dealing with devices between requester and co mpleter that can only stream data of 128 to 512 bytes due to buffering constraints, the peb383 uses ?short term caching.? this feature provides a time-limited read data cache in which the peb383 will not discard prefetched read data after the request completes on the initiating bus. to enable short term caching, set the stc_en bit in the ?pci miscellaneous control and status register? . when enabled, the peb383 does not discard th e additional prefetched data when the read transaction completes on the initiating bus. the peb383 then continues to prefetch data up to the amount specified in the ?prefetch control register? . if the initiator generates a new transaction that requests the previously prefetched da ta, the peb383 returns that data. the peb383 discards data after some of the data for a request is returned to the initiator and one of the following conditions is met: ? short-term discard timer is expi red before the initiator has re quested additional data (see ?short-term caching period register? ). ? an upstream posted transaction is received on the pci interface 3.7 polarity inversion the peb383 supports polarity inversion. for info rmation on how to use this feature, see the peb383 board design guidelines . short-term caching should only be used in sy stems that can ensure the data provided to the master has not been modified since the initial transaction. 29 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4. addressing topics discussed include the following: ? ?overview? ? ?memory-mapped i/o space? ? ?prefetchable space? ? ?i/o space? ? ?vga addressing? ? ?isa addressing? ? ?non-transparent addressing? ? ?legacy mode? 4.1 overview this chapter discusses th e various types of address decoding performed by the peb383 when it forwards transactions upstream and downstream. the memory and i/o addr ess ranges are defined using a set of base and limit registers in the bridge ?s configuration header. the base and limit address registers define the address ranges that a bridge forwards downstream transact ions. these registers are effectively inversely decoded to determine the addres s ranges on the pci interf ace for transactions that are forwarded upstream to the pcie interface. 4.2 memory-mapped i/o space memory transactions are forwarde d across the peb383 when their address falls within a window defined by one of the following registers: ? ?pci memory base and limit register? ? ?pci pfm base and limit register? the memory-mapped i/o address spacing maps me mory address ranges of devices that are not prefetchable. for pci to pcie reads, prefetching occurs in this space only if the memory read line or memory read multiple commands are issued on the pci bus. when ei ther of these commands is used, the quantity of data prefetch ed is determined by the pref etching algorithm defined in ?prefetching algorithm? . for pcie-to-pci, the number of bytes to read is determined by the memory read request tlp. 4. addressing > memory-mapped i/o space 30 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the response of the bridge to memory-mapped i/ o transactions is cont rolled by the following: ?ms bit in ?pci control and status register? ? this bit must be set to allow memory transactions to be forwarded downstream. if not set, all memory transactions on the pci bus are forwarded to the pcie link. in addition, if not set, all memory re quests on the pcie interface are completed with an unsupported re quest status. ? bm bit in ?pci control and status register? ? this bit must be set to allow memory transactions to be forwarded upstream. if this bit is not set, all memory transactions on the pci bus are ignored. ? vga_en bit in ?pci bridge control and interrupt register? the peb383 forwards memory trans actions downstream from its pcie interface to its pci interface if a memory address is in the range defined by the me mory base and memory limit registers (when the base is less than or equal to the limit), as shown in figure 9 . a memory transaction on the pci interface that is within this address range, however, is not be forwarded upstream to the pcie interface. any memory transactions on the pci interface that are outside this addr ess range are forwarded upstream to the pcie interface (provided they are not in the ad dress range defined by the set of prefetchable memory address registers). figure 9: memory-mapped i/o address space memory base memory limit p rimary interface downstream upstream memory base memory limit p rimary interface downstream upstream 4. addressing > prefetchable space 31 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the memory-mapped i/o address range that is defi ned by the base and limit registers are always aligned to a 1-mb boundary and has a size granularity of 1 mb. 4.3 prefetchable space the prefetchable address space maps memory address ranges of devices that ar e prefetchable; that is, devices that do not have side-effects during reads. for pci-to-pcie reads, prefetching occurs in this space for all memory read comman ds (memrd, memrdline, memrdmult) issued on the pci bus. for these read commands, the peb383 prefetches data according to pr efetching algorithm defined in ?prefetching algorithm? . for pcie-to-pci reads, th e number of bytes to be read is determined by the memory read request. the prefetchable memory base, prefetchable memory limit, prefetchable base upper 32 bits, and prefetchable limit upper 32 bits re gisters in the bridge configurati on header specify an address range that is used by the bridge to determine whether to forward pcie and pci memory read and memory write transactions across the bridge. the prefetchable memory a ddress range defined by these registers is always aligned to a 1-mb boundary and has a si ze granularity of 1 mb. if the address specified by the prefetchable memory base and prefetchable base upper 32 bits registers is set to a value higher than the address specified by the prefetchable me mory limit and prefetchable limit upper 32 bits registers, the address range is disabled. following register bits effe ct the response by the bridge to memory transactions: ? memory enable bit in ?pci control and status register? ? bus master enable bit in ?pci control and status register? ? vga enable bit in ?pci bridge control and interrupt register? the peb383 forwards memory trans actions downstream from its pcie interface to its pci interface if a memory address is in the range defined by the pr efetchable memory base and prefetchable memory limit registers. conversely, a memory transaction on the pci interface that is within this address range is not be forwarded upstream to the pcie interface. any memory transactions on the pci interface that are outside this address range are forwarded upstream to the pcie in terface (provided they are not in the address range defined by the memory -mapped i/o address range registers). if the prefetchable memory base is programmed to ha ve a value greater than the prefetchable memory limit, then the prefetchable memory range is disabl ed. in this case, all memo ry transaction forwarding is determined by the memory-mapped i/o base and limit registers. note that all four prefetchable base and limit registers must be considered when disabling the prefetchable range. unlike non-prefetchable memory-mapped i/o memory , prefetchable memory can be located below, above, or span across the fi rst 4-gb address boundary. figure 10 illustrates a prefetchable memory window that spans across the 4-gb address bounda ry. memory locations above 4 gb are accessed using 64-bit addressing. pcie memo ry transactions that use the sh ort address (32-bit) format can target a non-prefetchable memory window or the por tion of a prefetchable memory window that is below the first 4-gb address boundary. memory trans actions that use the long address (64-bit) format can target the portion of a prefetchable memory wi ndow that is at or abov e the first 4-gb address boundary. 4. addressing > i/o space 32 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 10: 64-bit prefetchable memory address range 4.4 i/o space i/o base, i/o limit, i/o base up per 16 bits, and i/o limit upper 16 bits registers in the peb383 configuration header speci fy an address range that is used by the bridge to determine whether to forward i/o read and i/o write tran sactions across the bridge. if the address specified by the i/o base and i/o base upper 16 bits registers is set to a valu e greater than the address specified by the i/o limit and i/o limit upper 16 bits register s, the address range is disabled. the response of the bridge to i/o transactions is controlled by the following configuration register bits: ? i/o space enable bit in ?pci control and status register? ? bus master enable bit in ?pci control and status register? ? isa enable bit in ?pci bridge control and interrupt register? ? vga enable bit in ?pci bridge control and interrupt register? the i/o enable bit must be set for any i/o transaction to be forwarded downstream. if this bit is not set, all i/o transactions on the pci bus are forwarded to the pcie link. if this bit is not set, all pcie interface i/o requests are complete d with unsupported request status. p rimary interface downstream upstream memory mapped i/o 4 gb boundary 4 gb boundary secondary interface prefetchable memory p rimary interface downstream upstream memory mapped i/o 4 gb boundary 4 gb boundary secondary interface prefetchable memory 4. addressing > i/o space 33 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the bus master enable bit must be set for any i/o transaction to be forwarded upstream. if this bit is not set, all i/o transactions on the pci bus are ignored. if isa enable bit is set, the bridge does not forward any i/o transactions downstream that are in the top 768 bytes of each 1-kb block within the first 64 kb of address space. only tran sactions in the bottom 256 bytes of each 1-kb block are forwarded down stream. if the isa enable bit is clear, then all addresses within the range defined by the i/o base and limit registers are forwarded downstream. i/o transactions with addresses above 64 kb are forwar ded according to the range defined by the i/o base and limit registers. if the isa enable bit is set, the bridge forwards upstream any i/o transactions on the pci bus that are in the top 768 bytes of each 1- kb block within the first 64 kb of address space, even if the address is within the i/o base and limi t. all other transactions on the pci bus are forwarded upstream if they fall outside the range defined by th e i/o base and limit registers. if the isa enable bit is clear, then all pci bus i/o addr esses outside the range de fined by the i/o base and limit registers are forwarded upstream. a bridge uses the i/o base and i/o limit registers to determine whether to forward i/o transactions across the bridge, as shown in figure 11 . the i/o address range defined by these registers is always aligned to a 4-kb boundary and has a size granular ity of 4 kb. a bridge fo rwards i/o read and i/o write transactions from its pcie interface to its pci interface if the address is in the range defined by the i/o base and i/o limit registers (when the base is less than or equal to the limit). conversely, i/o transactions on the pci bus in the address range de fined by these registers ar e not forwarded upstream by the bridge. i/o transactions on the pci bus that are outside the defined address range are forwarded upstream. 4. addressing > vga addressing 34 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 11: i/o address space 4.5 vga addressing the peb383 supports vga addressing. the vga_en bit in the ?pci bridge control and interrupt register? controls the response by the bridge to both vga frame buffer addresses and to vga register addresses. if the vga enable bit is set, the brid ge decodes and forwards memory accesses to vga frame buffer addresses and i/o accesses to vga re gisters from the pcie interface to the pci interface (and block forwarding from pci to pcie of these same accesses). the vga_16bit_en bit in the ?pci bridge control and interrupt register? selects between 10-bit and 16-bit vga i/o address deco ding, and is applicable when the vga enable bit is 1. vga memory addresses are 0x0a_0000 through 0x0b_ffff secondary interface 0x0_c000 ? 0x0_ffff 0x0_b000 ? 0x0_bfff 0x0_a000 ? 0x0_afff 0x0_9000 ? 0x0_9fff 0x0_8000 ? 0x0_8fff 0x0_0000 ? 0x0_7fff p rimary interface downstream upstream secondary interface 0x0_c000 ? 0x0_ffff 0x0_b000 ? 0x0_bfff 0x0_a000 ? 0x0_afff 0x0_9000 ? 0x0_9fff 0x0_8000 ? 0x0_8fff 0x0_0000 ? 0x0_7fff p rimary interface downstream upstream 4. addressing > isa addressing 35 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required vga i/o addresses (address bits 15:10 are not dec oded when the vga 16-bit decode bit is 0b) are: ? address bits 9:0 = 0x3b0 through 0x3bb and 0x 3c0 through 0x3df (vga 16-bit decode bit is 0b) ? address bits 15:0 = 0x03b0 thro ugh 0x03bb a nd 0x03c0 through 0x03df (vga 16-bit decode bit is 1b) the vga palette snoop enable bit is impleme nted as read-only with a value of zero. 4.6 isa addressing the peb383 supports isa addressing through isa enable bit in the ?pci bridge control and interrupt register? . the isa enable affects only i/o addresses that are in the bridge?s i/o range (as defined by the i/o base, i/o base upper 16 bits, i/o limit, and i/o limit upper 16 bits) and in the first 64 kb of pci i/o space (0000 0000h to 0000 ffffh). if this bit is set and th e i/o address meets the stated constraints, the peb383 blocks the forwarding of i/o transactions downstream if the i/o address is in the top 768 bytes of each naturally aligned 1-kb block. if the isa en able bit is clear, the peb383 forwards downstream all i/o addresses in the addr ess range defined by the i/o base and i/o limit registers. if the isa enable bit is set, i/o transactions on th e pci bus in the top 768 byt es of any 1-kb address block within the first 64 kb of pci i/o space is forw arded upstream, even if th e address is between the i/o base and i/o limit addresses. figure 12 illustrates this mapping for a 4-kb range. the isa enable bit only affects the i/o address decodi ng behavior of the bridge. it does not affect the bridge's prefetching, posting, ordering, or error handling behavior. 4. addressing > isa addressing 36 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 12: isa mode i/o addressing secondary interface 0x0_xd000 ? 0x0_xfff 0x0_xc00 ? 0x0_xcff 0x0_x000 ? 0x0_x0ff 0x0_x400 ? 0x0_x4ff 0x0_x800 ? 0x0_x8ff p rimary interface downstream upstream 0x0_x900 ? 0x0_x9ff 0x0_x500 ? 0x0_x7ff 0x0_x100 ? 0x0_x3ff secondary interface 0x0_xd000 ? 0x0_xfff 0x0_xc00 ? 0x0_xcff 0x0_x000 ? 0x0_x0ff 0x0_x400 ? 0x0_x4ff 0x0_x800 ? 0x0_x8ff p rimary interface downstream upstream 0x0_x900 ? 0x0_x9ff 0x0_x500 ? 0x0_x7ff 0x0_x100 ? 0x0_x3ff 4. addressing > non-transparent addressing 37 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4.7 non-transparent addressing at power-up, the host processor discovers the n eed for non-transparent bridging and enables the address remapping of prefetchable, non-prefetchable, and i/o ranges through c onfiguration. before enabling address remapping of the base and limit values, the remapped address ranges need to be programmed. the ?downstream non-transparent address remapping registers? allow downstream accesses to be mapped to arbitrary positions in pci memory space. while the memory base and limit registers always define th e range of addresses to be claimed on the pcie link and forwarded to the pci bus, cycles that are claimed have their addresses modified because of the difference in the base addresses of the windows on the two buses. 4.7.1 pcie to pci non-pref etchable address remapping downstream transactions that fall wi thin the address window defined by the ?pci memory base and limit register? are remapped according to the address window defined by the ?secondary bus non-prefetchable address remap control register? and ?secondary bus non-prefetchable upper base address remap register? . the following equations describe the address remapping process: ? prisecnpdiff = prinpbase - secnpbase, where ? prisecnpdiff : defines the difference between the pr imary non-prefetchable base and the secondary non-prefetchable base. ? prinpbase : defined in the previous paragraph. ? secnpbase : defined by ?secondary bus non-prefetchable address remap control register? and ?secondary bus non-prefetchable up per base address remap register? . ? secnpaddr = prinpaddr - prisecnpdiff, where ? secnpaddr : defines the remapped address that th e peb383 presents on the pci bus. ? prinpaddr : defines the address presented to the peb383 that falls within the registers described in the previous paragraph. ? prisecnpdiff : see previous bullet. 4.7.2 pcie to pci prefet chable address remapping downstream transactions that fall with in the address window defined by the ?pci pfm base and limit register? , ?pci pfm base upper 32 address register? , and ?pci pfm limit upper 32 address register? are remapped according to the address window defined by the ?secondary bus prefetchable address remap control register? and ?secondary bus prefetchable upper base address remap register? . the following equations describe the address remapping process: ? prisecpfdiff = pripfbase - secpfbase, where ? prisecpfdiff : defines the difference between the primary prefetchable base and the secondary prefetchable base. ? pripfbase : defined by the registers listed above. ? secpfbase : defined by ?secondary bus prefetchable address remap control register? and ?secondary bus prefetchable upper base address remap register? . 4. addressing > non-transparent addressing 38 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? secpfaddr = pripfaddr - prisecpfdiff, where ? secpfaddr : defines the remapped address th e peb383 presents on pci bus. ? pripfaddr : defines the address presented to the pe b383 that falls within the registers described in the previous paragraph. ? prisecpfdiff : see previous bullet. 4.7.3 pci to pcie address remapping because the addresses of the down stream memory windows on the pci bus have been shifted from their locations on the pcie link, th e address range of cycles that a br idge will not claim on the pci bus must also be shifted. therefore, memory cycles with addresses from secnpbase (see ?secondary bus non-prefetchable address remap control register? and ?secondary bus non-prefetchable upper base address remap register? ) to secnplimit or from secfpbase (see ?secondary bus prefetchable address remap control register? and ?secondary bus prefetchable upper base address remap register? ) to secfplimit will not be claimed by the bridge on the pci bus. the secondary bus non-prefetchable limit is described in the following equation: ? secnplimit = prinplimit - prisecnpdiff, where ? prinplimit : defined by ?pci memory base and limit register? and the additional ?primary bus non-prefetchable uppe r limit remap register? . ? prisecnpdiff : defines the difference between the pr imary non-prefetchable base and the secondary non-prefetchable base. the secondary prefetchable limit is described in the following equation: ? secpflimit = pripflimit - prisecpfdiff , where ? pripflimit : defined by ?pci pfm base and limit register? and ?pci pfm base upper 32 address register? . ? prisecpfdiff : defines the difference between the primary prefetchable base and the secondary prefetchable base. once the address is claimed as de fined above, a memory cycle is forwarded from the pci bus to the pcie link with its address modi fied according to the non-transp arent address (ntma) remapping windows (see offsets 0x68 to 0x7c): ? ntma window remapping 4. addressing > non-transparent addressing 39 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the ntma secondary base (see ?ntma secondary lower base register? and ?ntma secondary upper base register? ) and ntma secondary limit (see ?ntma secondary lower limit register? and ?ntma secondary upper limit register? ) define memory windows in the pci bus memory space that are mapped to arbitrary positions on the pcie link. the resulting location of the ntma window on the pcie link is defined by the following equations: ? prisecntmadiff = printmabase - secntmabase, where ? printmabase : defined by ?ntma control register? and ?ntma primary upper base register? . ? secntmabase : defined by ?ntma secondary lower base register? and ?ntma secondary upper base register? . ? printmalimit = secntmalimit + prisecntmadiff, where ? secntmalimit : defined by ?ntma secondary lower limit register? and ?ntma secondary upper limit register? . ? prisecntmadiff : see previous bullet. a memory cycle whose address fall s within a ntma window on the pci bus will have its address on the pcie link modified by the following equation: ? printmaaddr = secntmaaddr + prisecntmadiff, where ? secntmaaddr : secondary ntma address, which must fall within the window defined by the ntma secondary base and limit registers. ? prisecntmadiff : see previous bullet. transactions that are claimed on pci interface , and which are outside the ntma window, are forwarded upstream without address remapping. software should ensure that the location of the ntma window on the pci bus is outside of the pci bus memo ry windows, and that the ntma window on the pcie link is outside of the pcie link memo ry windows, or undefined operation may result. figure 13 displays an example of memory window remapping. 4. addressing > non-transparent addressing 40 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 13: memory window remapping example i/o address remapping the ?pci i/o address upper 16 register? in the peb383 configuration sp ace indicates the number of upper bits of the i/o address that are not used when forwarding downstream i/o space cycles to the pci bus. this allows i/o addresses to be translated down into the address range that is available on the pci bus. there is no enable bit for i/o address remappin g; any non-zero value in this register remaps the i/o transactions to a different address lo cation, as described in this section. ntma window prefetchable window non-prefetchable window ntma window prefetchable window non-prefetchable window pcie address space pci address space 8000_0000 bfff_ffff 3fff_ffff 0000_0000 9_c00_0000 a_ffff_ffff c000_0000 1_ffff_ffff c_c000_0000 c_ffff_ffff 4000_0000 7fff_ffff 4. addressing > legacy mode 41 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4.8 legacy mode when the peb383 is in legacy mode it supports subtractive decode. th is is a non-standard feature that is enabled through the legacy bit in the ?pci miscellaneous clock straps register? . when the peb383 is in legacy mode, all mwr, mrd, iowr, and iord transactions received on the upstream port (pcie) that do not decode to an internal address are forwarded to the pci interface. when the device is not in legacy mode, tlps that do not fall between the base and limit registers are handled as unsupported requests (ur). when the legacy bit is set, the prog field of ?pci class register? is changed to 0x1, indicating to software that a subtract ive bridge is present. when the legacy bit is set all pc ie capabilities are hidden from so ftware, and the following occurs: 1. next pointer in ?pci power management capability register? is set to 0, indicating it is the last capability 2. ?pcie capability registers? are treated as reserved 3. ?advanced error reporting capability registers? are treated as reserved 4. extended configuration regi sters are treated as reserved tip when the peb383 is configured in legacy mode , the pcie root port must also be configured to support subtractive decode. 4. addressing > legacy mode 42 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 43 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 5. configuration transactions topics discussed include the following: ? ?overview? ? ?configuration transactions? ? ?pcie enhanced configuration mechanism? ? ?configuration retry mechanisms? 5.1 overview each device in a pcie or pci system has a config uration space that is acc essed using configuration transactions in order to define its operational characteristics. this chapter describes how the peb383 handles pcie configuration requests. 5.2 configuration transactions there are two types of configuration transactio ns: type 0 and type 1. type 0 configuration transactions access the peb383?s internal config uration registers, while type 1 configuration transactions access devices that reside downstream of the peb383. type 1 transactions are converted to type 0 transactions if they target devices that reside on the downstream peb383 bus. if the transaction is intended for a device that is downstream of the bus directly below the peb383, the transaction is passed through the peb383 as a type 1 configuration transaction. if the transaction is not targeted for the peb383 or any device below the peb383, the tran saction is rejected. conf iguration transactions are only initiated by the root complex in pcie-based systems. configuration address formats are as follows. figure 14: pcie configuration address format reserved register address extended register address reserved function number device number bus number 1 0 7 2 11 8 15 12 18 16 23 19 31 24 reserved register address extended register address reserved function number device number bus number 1 0 7 2 11 8 15 12 18 16 23 19 31 24 5. configuration transactions > configuration transactions 44 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 15: pci type 0 configuration address format figure 16: pci type 1 configuration address format 5.2.1 type 0 configur ation transactions the peb383 responds to pcie type 0 configuration transactions that address its configuration space. this type of transaction configures the peb383 an d is not forwarded downstream. the peb383 ignores type 0 configuration transactions that originate on the pci interface. if a type 0 configuration cannot be processed, the peb383 handles it as an unsupported request. 5.2.2 type 1 configur ation transactions pcie type 1 configuration transacti ons are used for device configurat ion in a hierarchical bus system. the bus number field contained in the header of a type 1 conf iguration transaction specifies a unique pci bus in the pci bus hierarchy. the peb383 compar es the specified bus numb er with two register fields ? secondary bus number and subordinate bus number in ?pci bus number register? ? that are programmed by system software or firmware to determine whether or not to forward a type 1 configuration transactio ns across the bridge. unique address (ad[31:16]) corresponding to a particular device number) 31 16 00 register number function number reserved 1 0 7 2 10 8 15 11 unique address (ad[31:16]) corresponding to a particular device number) 31 16 00 register number function number reserved 1 0 7 2 10 8 15 11 device number 15 11 reserved 31 24 01 register number function number bus number 1 0 7 2 10 8 23 16 device number 15 11 reserved 31 24 01 register number function number bus number 1 0 7 2 10 8 23 16 5. configuration transactions > configuration transactions 45 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required if a type 1 configuration transaction is received on the pcie interface, the following sequence of tests is completed on the bus number field to determine how the peb383 should handle the transaction: 1. if the bus number field is equal to the se condary bus number value and the conditions for converting the transaction into a special cycle transaction are met, the peb383 forwards the configuration request to its pci interface as a sp ecial cycle transaction. if the conditions are not met, the peb383 forwards the co nfiguration request to the pci in terface as a type 0 configuration transaction. 2. if the bus number field is not equal to the seco ndary bus number value but is in the range of the secondary bus number and the subordinate bu s number (inclusive) values, the type 1 configuration request is specifying a bus number th at is located behind the bridge. in this case, the peb383 forwards the configuration request to the pci interface as a type 1 configuration transaction. 3. if the bus number field does not satisfy the te sts 1 and 2, the type 1 configuration request indicates a bus number that is not located behind the bridge. in this case, the configuration request in invalid and peb383 handles th is as an unsupported request. 5.2.3 type 1 to type 0 conversion if a pcie type 1 configuration transaction?s bus nu mber field is equal to the secondary bus number value, and the conditions for conversion to a sp ecial cycle transaction are not met, the peb383 forwards the transaction to the pci bus as a type 0 configuration transaction. in this case, a device connected to the pci interface of th e bridge is the target of the ty pe 0 configuration transaction. to translate and convert a pcie type 1 configur ation transaction to a pci type 0 configuration transaction, the peb383 does the following: ? sets address bits pci_ad[1:0] as 0b00 ? sets address bits pci_ad[7:2] the same as th e pcie transaction?s re gister address field ? sets address bits pci_ ad[10:8] the same as pcie tran saction?s function number field ? for a secondary bus operating in pci mode, it drives value 0b0000 on address pci_ad[15:11] ? for a secondary bus operating in pci, the peb3 83 check?s if the received extended register address field is zero. if this field is non-zero , the peb383 does not forw ard the transaction and treats it as an unsupported reques t on pcie and a received master-a bort on the destination bus. if the field is zero, the peb383 deco des the pcie device number field and asserts a single address bit in the range pci_ad[31:16] during the address phase (for device numbers in the range 0b0_0000 to 0b0_ 1111b). 5.2.4 type 1 to type 1 forwarding if a pcie type 1 configuration tran saction is received and the value specified by the bus number field is within the range of bus numbers between the secondary bus number (exclusive) and the subordinate bus number (inclusive), the peb383 forwards the transaction to its pci interface as a type 1 configuration transaction. in this case, the target of the transaction does not reside on the pci interface but is located on a bus segment further downstream. 5. configuration transactions > pc ie enhanced configuration mechanism 46 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required to translate the forwarded transaction from a pcie type 1 configuration request to a pci type 1 configuration transaction, th e peb383 does the following: ? sets address bits pci_ad[1:0] as 0b01 ? pci register number, function number, de vice number, and bus number (address bits pci_ad[23:2]) are generated directly ? that is, unmodified ? from the pcie configuration transaction?s register address, function nu mber, device number, an d bus number fields, respectively. ? checks if the received extended register addres s field is zero. if this field is non-zero, the peb383 does not forward the transaction and treats it as an unsupported request on pcie and a received master-abort on the destination bus. if the field is zero, the peb383 generates pci_ad[27:24] as 0b0000. 5.2.5 type 1 to special cycle forwarding when the peb383 receives a pcie type 1 configuratio n write request transaction, it converts it to a special cycle on its pci interf ace when the following conditio ns are met by the transaction: ? the bus number field matches the s econdary bus number register value ? the device number field is all ones (equals 0b1_1111) ? the function number field is all ones (equals 0b111) ? the register address and extended register address are both all zeros (equal 0b00_0000 and 0b0000, respectively). 5.3 pcie enhanced configuration mechanism the pcie enhanced configuration mechanism adds four additional bits to the register address field, thereby expanding the space to 4096 bytes. the pe b383 forwards configuration transactions only when the extended register address bits are all zero. this prevents address aliasing on the pci bus that does not support extended regi ster addressing. if a configurati on transaction targets the pci bus and has a non-zero value in the extended register address field, the peb383 handl es the transaction as if it received a master-a bort on the pci bus and then does the following: ? sets the appropriate status bits for the destination bus, as if the transaction had executed and resulted in a master-abort ? generates a pcie completion with unsupported request status 5. configuration transactions > configuration retry mechanisms 47 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 5.4 configuration retry mechanisms a pcie-to-pci bridge is required to return a completion for all conf iguration requests that cross the bridge from pcie to pci prior to expiration of the completion timeout timer in the root complex. this requires that bridges take ownership of all confi guration requests forwarded across the bridge. if the configuration request to pci completes successfu lly prior to the bridge?s timer expiration, the bridge returns a completion with norm al status on pcie for that reques t. if the configuration request to pci encounters an error condition prior to the br idge?s timer expiration, the bridge returns an appropriate error completion on pcie. if the config uration request to pci does not complete either successfully or with an error, prior to timer expi ration, the bridge is requi red to return a completion with configuration retry status (crs) on pcie for that request. after the peb383 returns a completion with crs on pcie, it continues to keep the configuration transaction active on the pci bus. for pci, the peb 383 keeps retrying the transa ction until it completes on the pci bus. when the configuration transactio n completes on the pci bus after the return of a completion with crs on pcie, the peb383 discards th e completion information. bridges that use this option are also required to implement brid ge configuration retry enable in the ?pcie device control and status register? . if this bit is cleared, the bridge does not return a completion with crs on behalf of configuration requests forwarded across the bridge. the lack of a completion results in eventual completion timeout at the root complex. 5. configuration transactions > configuration retry mechanisms 48 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 49 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6. bridging topics discussed include the following: ? ?overview? ? ?flow control advertisements? ? ?buffer size and management? ? ?assignment of requestor id and tag? ? ?forwarding of pcie to pci? ? ?forwarding of pci to pcie? ? ?pci transaction support? ? ?pcie transaction support? ? ?message transactions? ? ?transaction ordering? ? ?exclusive access? 6.1 overview the peb383 provides a connection path between a pc i bus and a pcie link. th e main function of the peb383 is to allow transactions be tween a master or a transmitter on one bus\link, and a target or a receiver on the other bus\link. the pci interface can operate in 32-bit pci mode up to 66 mhz. transactions flow through the peb3 83 can be classi fied as follows: ? pcie-to-pci ? pci-to-pcie 6.2 flow control advertisements the flow control method on the pci interface is managed through retries or disconnects, where as on the pcie link it is managed using flow control credits. on the pci interface, the peb383 issues retries to ne w request transactions and issues a disconnect for the active transaction if the internal request queues or data storage buf fers are full or approaching full. on pcie interface, the peb383 pe riodically conveys its availabl e buffer space to the other end component in terms of flow control credits using fl ow control packets. the peb383 advertises flow control credits as per pcie protocol requirements. 6. bridging > buffer size and management 50 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.3 buffer size and management the peb383 provides sufficient buffering to satisf y pcie bridging requiremen ts. the peb383 does not overcommit its buffers: it forwards requests onto the other side only when enough buffer space is reserved to handle the returned completions. the peb383 uses 1-kb retry buffer ing, which is large enough to ensure that unde r normal operating conditions upstream traffic is never throttled. ac k latency value, internal processing delays, and receiver l0s exit latency values, are consid ered for determining the retry buffer size. 6.4 assignment of requestor id and tag the peb383 assigns a unique transaction id for al l the non-posted requests forwarded to upstream devices. the peb383 takes ownership of the upstream transactions on behalf of original requestors, and stores the transaction-related state information needed to return the completions to the original requesters. the action of replacing the original transaction?s requeste r id and/or tag fields with the bridge?s own assigned values is referred to as taking ownership of the transaction. for upstream non-posted requests, the peb383 assi gns the pcie requester id using its secondary bus number and sets both the devi ce number and function number fiel ds to zero. for the upstream transactions, the peb383 sets the tag fi eld to a request enqu eued entry number. 6.5 forwarding of pcie to pci the peb383 forwards posted, non-posted, and upstr eam read completions to the pci devices, and stores the non-posted tlps? state information to return the completion tlps to the pcie interface. 6.5.1 pcie memory write request the peb383 forwards the received pcie memory write requests to the pci interface with either memory write (mw) or memory write and invalidate (mwi) comm and. the peb383 translates the request into a pci transaction using the mwi command if it meets the mwi command rules specified in the pci local bus specific ation (revision 3.0) , and the mwi bit is set in the ?pci control and status register? . an mw command is used for the remaining part of the mwi transaction if the transaction is disconnected such that the rema ining request does not meet th e mwi command rules. the peb383 does not support relaxed ordering among the received requests. it fo rwards all requests in the order they are received even if the relaxed orde ring bit is set for some of the requests. 6.5.2 pcie non-posted requests the peb383 translates the pcie me mory read requests into pci tran sactions that use a pci memory read command (that is, memory read, memory read line, or memory read multiple) based on its cacheline size value, requ ested byte enables, and prefetchable an d non-prefetchable memory windows. pcie read request command translation is completed as follows: ? memory read if the pcie request falls into th e non-prefetchable address range defined by the ?pci memory base and limit register? . 6. bridging > forwarding of pci to pcie 51 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? memory read line if the pcie request falls into the prefet chable range defined by the ?pci pfm base and limit register? , and the requested data size is less th an or equal to the value specified in cacheline size of the ?pci miscellaneous 0 register? . ? memory read multiple if the pcie request fall s into the prefetchable range defined by the ?pci pfm base and limit register? , and the requested the data size is greater than or equal to the value specified in cach eline size of the ?pci miscellaneous 0 register? . the peb383 supports a single outstanding request. it does not attempt to read beyond the requested length. the peb383 decompos es the requests if the requested data length is greater than 128 bytes, and returns the completions in 128-byte boundary fragments. the peb383 uses pci byte enable fields such that the byte enable information is preserved and no additional bytes are requested for th e transactions that fall into th e non-prefetchable address range (for example, configuration, i/o, and memory read commands). 6.6 forwarding of pci to pcie the peb383 forwards posted and non-posted reques ts and downstream read completions to pcie devices, and stores th e non-posted requests ? state information to return the delayed completions to the requester. 6.6.1 pci memory write request the peb383 translates the receiv ed memory write (mw) and memo ry write and invalidate (mwi) transactions into pcie memory write requests. th e peb383 uses a 512-byte posted buffer to post the received transactions. write reques ts are fragmented if one of the following pcie c onstraints is met: ? address plus length crosses the 4-kb boundary ? burst writes with discontinuous byte enables ? payload size exceeds max_pay_size in ?pcie device control and status register? the peb383 terminates a posted transa ction with retry only if the buffers are filled with previously received memory requests, or if the brid ge is locked from the pcie side (see ?locked transaction? ). for more information on locked accesses, see ?exclusive access? . 6. bridging > forwarding of pci to pcie 52 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.6.2 pci non-posted requests the peb383 processes all non-posted transactio ns as delayed transactions. the peb383 first terminates the received non-posted tr ansaction with retry and then forw ards it onto the pcie interface. the peb383 stores the request-re lated state information while forw arding the request onto the pcie interface. this information tracks th e requests repeated by the master and returned completions for the request. since pci read requests do not specify the amount of data to be read, the peb383 uses a programmable prefetch algorithm to determine the amount of data to be read on behalf of the original requester. the peb383 does not attempt to prefetch past the 4-kb address boundary on behalf of the original requester. the peb383 stor es the returned completion until th e pci requester repeats the initial request and terminates th e delayed transaction. if short-term caching is enable d (see stc_en in ?pci miscellaneous control and status register? ), the peb383 responds to su bsequent requests with the incremental addresses issued by the master until th e programmed number of data bytes are transferred to the master or the short-term discar d timer is expired (see st_dist_en in ?serrdis_opqen_dtc register? ). the peb383 enqueues up to four requests and issues the initial requests on the pcie interface in the order they were received; however, the ordering is not guaranteed for the s ubsequent requests of decomposed transactions. the peb383 discards the enqueued delayed request if the requested data is not returned before the completion timeout is expired (see ?completion timeout register? ), and returns a delayed completion with target abort to the requester (see discard2 in ?pci bridge control an d interrupt register? ). a delayed completion is discarded if the requester does not repeat the initial request or if the requester disconnects the delayed completion af ter few data bytes are transferred. 6. bridging > pci transaction support 53 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.7 pci transaction support the following table lists the transactions supported by the pci interface. table 10: pci transaction support cmd transaction a a. for unsupported transactions, see ?pcie as originating interface? . pci interface as a master as a target 0000b interrupt acknowledge na na 0001b special cycle yes na 0010b i/o read yes yes 0011b i/o write yes yes 0100b rsvd na na 0101b rsvd na na 0110b memory read yes yes 0111b memory write yes yes 1000b rsvd na na 1001b rsvd na na 1010b configuration read yes na 1011b configuration write yes na 1100b memory read multiple yes yes 1101b dual address cycle yes yes 1110b memory read line yes yes 1111b memory write and invalidate yes yes 6. bridging > pcie transaction support 54 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.8 pcie transaction support the following table lists the transactions supported by the pcie interface. table 11: pcie transaction support tlp type transaction a a. for unsupported transactions, see ?pcie as originating interface? . pcie interface as a transmitter as a receiver mrd memory read request yes yes mrdlk memory read request locked na yes mwr memory write request yes yes iord i/o read request yes yes iowr i/o write request yes yes cfgrd0 configuration read type 0 na yes cfgwr0 configuration write type 0 na yes cfgrd1 configuration read type 1 na yes cfgwr1 configuration write type 1 na yes msg message request yes yes msgd message request with data payload na yes msgd (vendor defined) vendor-defined message request with data payload no no cpl completion without data yes yes cpld completion with data yes yes cpllk completion without data for mrr- locked yes na cpldlk completion with data for mrr - locked yes na 6. bridging > message transactions 55 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.9 message transactions message transactions are used for in-band communicati on of events, and theref ore, eliminate the need for sideband signals. pcie messag es are routed depending on specific bit field encodings in the message request header. 6.9.1 intx inte rrupt signaling the peb383 forwards the intx inte rrupts ? pci_int[a:d]n ? generate d by pci devices onto the pcie interface, as pcie as sert_intx and deassert_ intx messa ges (for more information, see ?interrupt handling? ). 6.9.2 power management power management messages support power mana gement events (pme) signaled by sources integrated into the bridge and for devices downstr eam of the bridge. the peb383 forwards the power management events (pci_pmen) from pci devices on to the pcie interface us ing pcie pme messages (for more information, see ?power management event? ). 6.9.3 locked transaction unlock messages support locked transaction sequen ces in the downstream di rection. this type of message indicates the end of a locked sequence. the peb383 supports locked transactions in the downstream direction an d uses unlocked messages to unlock itself from the pcie interface (see ?exclusive access? ). 6.9.4 slot power limit these messages are transmitted to downstream devi ces by the root complex or a switch. the peb383 copies the set slot power limit payload into the set slot power limit scale and set slot power value fields of the ?pcie device capabilities register? . 6.9.5 vendor-defined and device id these messages are used for vendor-specific purp oses. the peb383 does not support forwarding of these messages. it terminat es device id message transactions on the pci interface with master-abort. it silently discards the vendor-defined type 1 me ssage tlps and handles the vendor-defined type 0 message tlps as un supported requests. the peb383 ignores the receipt of ignored messages. it handles the receipt of error signaling messages as unsupported requests. the peb383 handles the receipt of intx messag es as malformed tlps. 6. bridging > transaction ordering 56 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.10 transaction ordering table 12 defines the transaction orderi ng rules that are followed by the peb383. these rules apply uniformly to all types of transactions, includ ing memory, i/o, configurations, and messages. in the table, the columns represen t a first received trans action while the rows re present a subsequently received transaction. each table entry indicates the ordering relati onship between the two transactions. the table entries are defined as follows: ? yes ? the second transaction is allowed to pass the first transaction. ? no ? the second transaction is not allowed to pass the first transaction. the peb383 does not allow a posted transaction to pass another posted transaction even if the relaxed ordering attribute bit is set. however, the device al lows a read completion with the relaxed ordering attribute bit set to pass a posted transaction. table entries with 1) and 2) are defined as follows: 1. indicates the ordering relationship when the re laxed ordering attribute bi t is clear in the second transaction header information. 2. indicates the ordering relationsh ip when the relaxed ordering attribute bit is set in the second transaction header information. table 12: transaction ordering posted request non-posted request completion can row pass column? memory write or message request read request i/o or configuration write request read completion i/o or configuration write completion posted request memory write or message request 1) no 2) no yes yes 1) yes 2) yes 1) yes 2) yes non-posted request read request no yes yes yes yes i/o or configuration no yes yes yes yes completion read completion 1) no 2) yes yes yes 1) yes 2) yes yes i/o or configuration write completion no yes yes yes yes 6. bridging > exclusive access 57 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6.11 exclusive access thepeb383 provides an ex clusive access method, which allows non-exclusive accesses to proceed while exclusive accesses take place. this allows a master to hold a hardware lock across several accesses without interfering with non-exclusive da ta transfer. locked tr ansaction sequences are generated by the host processor(s) as one or more r eads followed by a number of writes to the same location(s). the peb383 supports lo cked transactions only in the downstream direct ion. upstream lock transactions are handled w ith the lockn signal ignored. a lock is established when all the following conditions are met: ? a pcie device initiates a memory read lock (m rdlk) request to read from a target pci device ? lockn is asserted on the pci bus ? the target pci device responds with a trdyn the bus is unlocked when the unlock message tlp is received on the pcie link. thepeb383 enters into target-lock state when it recei ves a mrdlk tlp, and enters into full-lock state when it receives successf ul completion from the ta rget device. thepeb383 attempts locked read request on the pci bus only after all the requests re ceived prior to the locked request are completed on the bus. while in target-lock state, thepeb383 handles all the received tlps with ur but continues to accept the transactions on the pci interface. when thepeb383 enters into full-l ock state, all upstream transactio ns on the pci interface are retried and all the downstream requests on the pcie interface, except memory transactions, are handled as ur. requests pending in upstream queues or buffers and internally generated messages are not allowed to be forwarded to the pcie interface until thepeb 383 is unlocked from the pcie interface. however, thepeb383 accepts read completions for upstream read requests that were issu ed before the lock was established on the pci bus when they return on the pcie link. as soon as the pci bus is locked, any pcie cycle to pci is driven with the pci_lockn pin asserted, even if that specific cycle is no t locked. this is not expected to occur because under the lock, the upstream component must not send an y non-locked transactions downstream. during the lock sequence, when the initial locked read command results in a master or target abort on the pci bus, thepeb383 does not establish lock, and it sends a completion packet on the pcie link with an error status. in ca se of a subsequent memory read or memo ry write receiving a target or master abort during a lock sequence, thepeb383 unlocks only after the unlock message is received on the pcie interface. 6. bridging > exclusive access 58 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 59 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 7. pci arbitration topics discussed include the following: ? ?overview? ? ?block diagram? ? ?pci arbitration scheme? 7.1 overview the pci internal bus arbiter manages access to the pci bus for up to five re questers, including the peb383. the bus arbiter has the following features: ? supports five requests (four external and one internal, the peb383) ? can be programmed to give high and low priorities for requesters ? bus is parked on late st master given grant 7.2 block diagram the bus arbiter handles internal re quests from the pci core and extern al requests from devices on the pci bus (see figure 17 ). when the arbiter is enabled, the peb3 83 asserts the grant for pci devices and for the pci core. when the arbiter is disabled, there must be an external arbiter on the pci bus that handles peb383 requests through the pci_req[ 0]n signal, and grants bus access using the pci_gnt[0] signal. grants and requests are bi-directional pins. pci_req[ 0]n is output enabled wh en the internal arbiter is disabled. enable of pci_req[3:1]n are always hardcoded to 1?h0. pci_gn t[0] is an input pin when the internal arbiter is disabled. figure 17: pci arbiter block diagram 7. pci arbitration > pci arbitration scheme 60 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 7.3 pci arbitration scheme the arbiter can be programmed to enable or di sable, and prioritize, each requester using the ?pci miscellaneous control and status register? . the peb383, by default, is assigned a high priority and the other requesters ar e assigned a low priority. based on the priority setting, requ esters are divided into two groups of high and low priority. within a group, priority is determined using a round-robin method (see figure 18 ). the low-priority group is handled as one member of the high-priority group. by default, the pci arbiter initially parks the bus on the peb383. after servicing the requesters when the bus is in idle state, the arbiter is parked on the last served requester. the priority method is shown in figure 18 . note that any one request in put can only be mapped to high or low priority. if, for example, pci_req2n is mapp ed to low priority, then the h2 state is skipped over. figure 18: pci arbitration priority the peb383 also keeps track of which requestor, in each priority group, was last served. this is achieved with two arbitration pointers, one for each priority. when a new requestor is granted the bus, the pointer(s) advance. this gives each requestor a fair chance of being select ed first when multiple requestors request the bus. note : any device can be high or low priority; however, a device can have only one priority setting as defined by the pci_misc_csr register. l h-peb38x h0 h3 h2 h1 high priority l1 l2 l0 l-peb38x l3 low priority 7. pci arbitration > pci arbitration scheme 61 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required this is shown conceptually in figure 19 . here the last served high priority device is h1, and the last served low priority device is l2. when the high priority pointer is at h1 , the order of priority is h2, h3, low, h-peb383, h0, and h1. figure 19: arbitration pointers ? example 1 when the transaction for device 1 is complete, all input requests are sampled to determine which device should be granted next. if there are no reques ts the pointer stays at h1 , and no grants are given. if two requests occur at the same time ? in this ex ample, l3 and h1 ? then l3 is granted and the pointers advance as shown in figure 20 . figure 20: arbitration pointers ? example 2 once l3 is completed, the input requests are sample d again. h0 and h1 are now requesting the bus. h0 would then obtain access to the bu s because the new priority orderi ng is h-peb383, h0, h1, h2, h3, l. the initial ordering of the requests is not consider ed; that is, h1 requested be fore h0, but h0 wins as it is first in the priority list. this ensures that all requestors obtain equal access within a priority group. after asserting the grant, if the bus is in an idle state for m clock cycles grant is de-asserted. h-peb38x high priority h0 h1 h2 h3 l l-peb38x low priority l0 l1 l2 l3 h-peb38x high priority h0 h1 h2 h3 l l-peb38x low priority l0 l1 l2 l3 7. pci arbitration > pci arbitration scheme 62 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 63 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 8. interrupt handling topics discussed include the following: ? ?overview? ? ?interrupt sources? ? ?interrupt routing? 8.1 overview the peb383 supports the two types of interrupts that originate on a pci bus: ? legacy pci interrupts, pci_int[d:a]n ? message-based interrupts ? message signaled interrupts (msi) ? enhanced message signale d interrupts (msi-x) the peb383?s pci interface forwards legacy intx assertion/de-asserti ons in the form of assert_intx and deassert_intx messages on its pcie link. the peb383 handles msi and msi-x transactions as pci memory write transactions. when the bri dge receives an msi/msi-x transaction on its pci interface, it forwards it as a memory write tlp on its pcie link. both intx messages and msi/msi-x transactions flow through the peb 383?s upstream posted buffe r, as displayed in figure 21 . figure 21: interrupt handling diagram upstream posted buffer pci target interface pci_intan pci_intbn pci_intcn pci_intdn interrupt message generation 8. interrupt handling > interrupt sources 64 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the interrupt message generati on module connects to the pc i target interface, external pci_int[d:a]n interrupts, and th e upstream posted buffer (see figure 21 ). assertion and de-assertion of interrupts are stored in the fo rm of assert_intx and deassert_i ntx flags. these flags are kept asserted until the posted buffer ca n handle corresponding assert and de -assert messages. if an interrupt pin is toggled when the pci interfa ce is engaged with a pci-initiated posted transaction, assert or de-assert message loading into the upstream posted re quest buffer is stalled un til the upstream posted transaction terminates. posted tran sactions are retried on the ad bu s while an interrupt message is loaded into the posted buffer. a de-assert message always follows an assert message. more then one interrupt pin can toggle at any point of time; however, a round-robin arbitration schedules the interrupt message transmission. there is no buffering for interrupt messages before loading them into the upstream posted buffer. therefore, only one pair of assert_intx and dea ssert_intx messages is loaded into the buffer when allowed. in the worst case, the bridge may send duplicate messages; howeve r, this is permitted according to the pci express base specification (revision 1.1) . 8.2 interrupt sources the peb383 does not have an internal source of interrupts: it forwards legacy pci_int[d:a]n interrupts from the pci interface to the pcie interf ace in the form of assert [d:a] and de-assert[d:a] messages with peb383 pcie transaction ids. 8.3 interrupt routing interrupt remapping is not performe d by the peb383. legacy interrupts, pci_int[a:d]n, are routed to the upstream pcie port in the form of assert_intx and deas sert_intx [a,b,c,d] messages. 65 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9. error handling topics discussed include the following: ? ?overview? ? ?pcie as originating interface? ? ?pci as originating interface? ? ?timeout errors? ? ?other errors? ? ?error handling tables? 9.1 overview this chapter discusses how the peb 383 handles errors that occur duri ng the processing of upstream and downstream transactions. for all errors that are detected by the bridge, it sets the appropriate error status bits ? pci error bit(s) and pcie error status bit(s) ? and generates an error message on pcie, if enabled. each error condition has an error severity level programmable by software, and a corresponding error message generated on pcie. each detected error cond ition has a default error severity level (fatal or non-fatal) and, when enabled, ha s a corresponding error message gene rated on pcie. the error severity level is software programmable. pcie link error message generation is controlled by the following bits: ?serr_en in the ?pci bridge control an d interrupt register? ?ftl_err_en in the ?pcie device control and status register? ? nftl_err_en in the ?pcie device control an d status register? ? cor_err_en in the ?pcie device control and status register? err_fatal pcie messages are enab led for transmission if either of the following bits is set: serr_en in ?pci control and status register? , or ftl_err_en in ?pcie device control and status register? . 9. error handling > overview 66 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required err_nonfatal messages are enabled for transmission if either of the following bits is set: serr_en in ?pci control and status register? , or nftl_err_en in ?pcie device control and status register? . err_cor messages are enabled for tran smission if cor_err_en is set in ?pcie device control and status register? . ftl_err_dtd, nftl_err_dtd, and cor_err_dtd bits in ?pcie device control and status register? are set for the corresponding errors on the pc ie interface, regardless of the error reporting enable bits. the peb383 also supports advisory non-fatal erro r messages in the case where a tlp error detected is a advisory non-fatal error and the adviso ry non-fatal error mask bit, anfe, in the ?pcie correctable error mask register? is not masked then a correctable error message is generated instead of a non-fatal error message. figure 22 depicts the high-level flowchar t for error handling on pcie. this is taken from table 6-2 of the pci express base speci fication (revision 1.1) , and includes advanced error handling. additional error handling requirements for a pcie bridge are described in subsequent sections of the specification. 9. error handling > overview 67 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 22: pcie flowchart of device error signaling and logging operations 9. error handling > pcie as originating interface 68 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9.2 pcie as originating interface this section describes how the peb383 handles erro r support for transactions that flow downstream from pcie to pci (see figure 23 ). in the case of reception of a write request or re ad completion with a poisoned tlp, the entire data payload of the pcie transaction is considered as corrupt and the parity is inverted on every data phase forwarded (see table 13 ). in the case of reception of a requ est with ecrc error, the entire tlp is considered as corrupt and is dropped by the bridge. figure 23: transaction error forwarding with pcie as originating interface table 14 provides the translation a bri dge has to perform when it forw ards a non-poste d pcie request (read or write) to pci and the request is complete d immediately on pci, either normally or with an error condition. table 13: error forwarding requirements (step a to step b) for received pcie errors received pcie error (step a) forwarded pci error mode 1 (parity) (step b) write request or read completion with poisoned tlp poisoned data parity request with ecrc (optional support) error do not forward table 14: bridge requirements for transactions requiring a completion (immediate response) immediate pci termination pcie completion status data transfer with uncorrectable data error (reads) successful (poisoned tlp) data transfer with uncorrectable data error (non-posted writes) unsupported request requ est or or delayed t ransacti on compl eter pe b 3 8 x immediat e complet er st e p a ste p b step d st e p c pc i (destination interface) pc i e (ori gi nating interface) 9. error handling > pcie as originating interface 69 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required in the case of an advisory non-fa tal error detection, the following actions are taken by the peb383: 1. if the severity of th e tlp error detected in ?pcie uncorrectable error severity register? is non-fatal then: a. cor_err_dtd is set in the ?pcie device control and status register? b. anfe is set in the ?pcie correctable erro r status register? 2. and if the anfe bit is not masked in the ?pcie correctable error mask register? then: a. tlp error status bit is set in the ?pcie uncorrectable e rror status register? b. if the corresponding tlp erro r mask bit is clear in the ?pcie uncorrectable error mask register? and err_ptr is not valid in the ?pcie advanced error capabilities and control register? , then the tlp header is logged in the ?pcie header log 1 register? and err_ptr is updated in the ?pcie advanced error capabi lities and control register? . c. if cor_err_en is set in the ?pcie device control and status register? then it sends a correctable error message. 9.2.1 received poisoned tlps when the bridge receives a poison ed tlp it completes the following while forwarding it to the pci interface: 1. if the severity of the ptlp in the ?pcie uncorrectable error severity register? is non-fatal and the anfe mask bit is clear in ?pcie correctable error mask register? then: ? a correctable error message is generated if the cor_err_en bit is set in the ?pcie device control and status register? ? anfe bit is set in the ?pcie correctable erro r status register? ? cor_err_dtd bit is set in the ?pcie device control and status register? ? ptlp bit is set in the ?pcie uncorrectable error status register? ? tlp header is logged in the header log regi ster and err_ptr is updat ed if the ptlp mask bit in ?pcie uncorrectable error mask register? is clear and the err_ptr is not valid 2. if the severity of the ptlp bit in ?pcie uncorrectable error severity register? is non-fatal and the anfe mask bit is set in ?pcie correctable error mask register? then: ? no error message is generated ? cor_err_dtd bit is set in the ?pcie device control and status register? ? anfe bit is set in the ?pcie correctable erro r status register? master-abort unsupported request target-abort completer abort table 14: bridge requirements for transactions requiring a completion (immediate response) immediate pci termination pcie completion status 9. error handling > pcie as originating interface 70 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 3. if it is not an afne then: ? fatal error message is generated if ptlp mask bit is clear in the ?pcie uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en bit is set in the ?pcie device control and status register? ? ftl_err_dtd bit is set in the ?pcie device control and status register? ? ptlp bit is set in the ?pcie uncorrectable error status register? ? tlp header is logged in the header log regi ster and err_ptr is updat ed if the ptlp mask bit is clear and the err_ptr is not valid. ? s_serr bit is set in the ?pci control and status register? if fatal error message is generated and the serr_en bit is set in the ?pci control and status register? . 4. in all three of the previous cases the foll owing actions are also taken by the peb383: ? d_pe bit is set in ?pci control and status register? ? mdp_d bit set in ?pci control and status register? if the poisoned tlp is a read completion and the peresp bit is set in the ?pci control and status register? ? parity bit is inverted on the pci bu s with each associated data dword ? mdp_d bit is set in the ?pci secondary status and i/ o limit and base register? if the s_peresp bit is set in the ?pci bridge control an d interrupt register? , and the bridge sees the pci_perrn pin asserted when forwarding a write request transaction with bad parity to the pci bus. the pe rr_ad bit in the ?pcie secondary uncorrectable error status register? is set, secondary header is logged and second ary first error pointer is updated if enabled. no error message is generated when pci_pe rrn is seen asserted by the bridge when forwarding a poisoned tlp transaction from pcie to pci with bad parity. 9.2.2 received ecrc errors when the peb383 receives a tlp with ecrc error, it does the following: 1. drops the transaction 2. d_pe is set in the ?pci control and status register? 3. ecrc bit is set in the ?pcie uncorrectable e rror status register? 4. header is logged in the ?pcie header log 1 register? and the err_ptr field is updated in the ?pcie advanced error capabili ties and control register? if ecrc error mask bit is clear in the ?pcie uncorrectable error mask register? and err_ptr is not valid. 5. error fatal or non-fatal message is generated on pcie as per the severity level of ecrc bit in ?pcie uncorrectable error severity register? if the ecrc mask bit is clear in ?pcie uncorrectable error mask register? , and either serr_en bit is set in the ?pci control and status register? or ftl_err_en/nftl_er r_en is set in the ?pcie device control and status register? 6. s_serr bit is set in the ?pci control and status register? if an error message (fatal/non-fatal) is generated and serr_en bit is set in the ?pci control and status register? 7. ftl_err_dtd/nftl_err_dtd bit is set in the ?pcie device control and status register? 9. error handling > pcie as originating interface 71 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9.2.3 pci uncorrectable data errors this section describes the bridge requirements for error handling when forwarding downstream a.non-poisoned pcie transaction to pc i and the bridge detects an uncorr ectable data error. the error is detected on the pci interface. 9.2.3.1 immediate reads when the peb383 forwards a read request (i/o, me mory, or configuration) downstream, it does the following when it detects an unco rrectable data error on the destin ation interface while receiving an immediate response from the completer: 1. mdp_d bit is set in the ?pci secondary status and i/ o limit and base register? if the s_peresp bit is set in the ?pci bridge control a nd interrupt register? 2. d_pe in the ?pci control and status register? is set 3. pci_perrn is asserted on the pci inte rface if the s_peresp bit is set in the ?pci bridge control and interrupt register? 4. uderr bit is set in ?pcie secondary uncorrectable error status register? 5. header is logged in the ?pcie secondary header log 1 register? and the sufep field is updated in the ?pcie secondary error capabili ties and control register? if uderr mask bit is clear in the ?pcie secondary uncorrectable error mask register? and sufep is not valid 6. error fatal or non-fatal message is generated on pcie as per the severity level of uderr bit in ?pcie secondary uncorrectable error severity register? if the uderr mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in the ?pci control and status register? or ftl_err_en/nftl_err_ en bit is set in the ?pcie device control and status register? 7. s_serr bit is set in the ?pci control and status register? if an error message (fatal/non-fatal) is generated and s_serr bit is set in the ?pci control and status register? 8. ftl_err_dtd/nftl_err_dtd bit is set in the ?pcie device control and status register? for an immediate read transaction, if the peb383 detects an uncorrectab le data error on the destination bus it continues to fetch data until the byte count is satisfied, or the target on the destination bus ends the transaction. when the bridge cr eates the pcie completion, it forwar ds it with successful completion status and poisons the tlp. 9.2.3.2 non-posted writes when the peb383 detects pci_perr n asserted on the pci interface while forwarding a non-poisoned non-posted write transaction from pcie, it does the following: 1. if the target completes the transaction immediat ely with a data transfer, the peb383 generates a pcie completion with unsupported request st atus to report the error to the requester 2. perr_ad bit is set in the ?pcie secondary uncorrectable error status register? 3. mdp_d bit in the ?pci secondary status and i/ o limit and base register? is set if s_peresp bit is set in the ?pci bridge control and interrupt register? 9. error handling > pcie as originating interface 72 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4. header is logged in the ?pcie secondary header log 1 register? and the sufep field is updated in the ?pcie secondary error capabili ties and control register? if perr_ad mask bit is clear in the ?pcie secondary uncorrectable error mask register? and sufep is not valid 5. error fatal or non-fatal message is generated on pcie as per the severity level of perr_ad bit in ?pcie secondary uncorrectable error severity register? if the perr_ad mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in the ?pci control and status register? or ftl_err_dtd/nftl_err_ dtd bit is set in the ?pcie device control and status register? 6. s_serr bit is set in the ?pci control and status register? if an error message (fatal/non-fatal) is generated and serr_en bit is set in the ?pci control and status register? 7. ftl_err_dtd/nftl_err_dtd bit is set in the ?pcie device control and status register? 9.2.3.3 posted writes when the peb383 detects pci_perr n asserted on the pci interface while forwarding a non-poisoned posted write transaction from pcie, it does the following: 1. continues to forward the remainder of the transaction 2. mdp_d bit in the ?pci secondary status and i/ o limit and base register? is set if s_peresp bit is set in the ?pci bridge control and interrupt register? 3. perrn assertion detected status bit is set in the ?pcie secondary uncorrectable error status register? 4. header is logged in the ?pcie secondary header log 1 register? and the sufep field is updated in the ?pcie secondary error capabili ties and control register? if perr_ad mask bit is clear in the ?pcie secondary uncorrectable error mask register? and sufep is not valid 5. error fatal or non-fatal message is generated on pcie as per the severity level of perr_ad bit in ?pcie secondary uncorrectable error severity register? if the perr_ad mask bit is clear in ?pcie secondary uncorrectable error mask register? , and either serr_en bit is set in the ?pci control and status register? or ftl_err_dtd/nftl_err_ dtd bit is set in the ?pcie device control and status register? 6. s_serr bit is set in the ?pci control and status register? if an error message (fatal/non-fatal) is generated and serr_en bit is set in the ?pci control and status register? 7. ftl_err_dtd/nftl_err_dtd bit is set in the ?pcie device control and status register? 9.2.4 pci uncorrectable address/attribute errors when the peb383 forwards transac tions from pcie to pci, address or attribute errors are reported through the pci_serrn pin. when the peb383 dete cts pci_serrn asserted it does the following: 1. continues forwarding transaction 2. s_serr system bit is set in the ?pci secondary status and i/o limit and base register? 3. serr_ad bit is set in the ?pcie secondary uncorrectable error status register? 4. in this case header is not logged but the sufep is updated in the ?pcie secondary error capabilities and control register? if the sufep bit is not valid and serr_ad mask bit is clear in the ?pcie secondary uncorrectable error mask register? 9. error handling > pcie as originating interface 73 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 5. error fatal or non-fatal message is generated on pcie as per the severity level of serr_ad bit in ?pcie secondary uncorrectable error severity register? if serr_ad mask bit is clear in ?pcie secondary uncorrectable error mask register? or serr_en bit is set in ?pci bridge control and interrupt register? , and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 6. s_serr bit is set in the ?pci control and status register? if an error message (fatal/non-fatal) is generated and serr_en bit is set in the ?pci control and status register? 7. ftl_err_dtd/nftl_err_dtd bit is set in the ?pcie device control and status register? 9.2.5 received master-a bort on pci interface this section describes the actions taken by the peb383 when a master-abort is received on the pci interface. 9.2.5.1 master abort on a posted transaction when the peb383 receives a master -abort on the pci bus while forw arding a posted write transaction from pcie, it does the following: 1. discards the entire transaction 2. r_ma bit is set in ?pci secondary status and i/ o limit and base register? 3. r_ma bit is set in the ?pcie secondary uncorrectable error status register? 4. header is logged in the ?pcie secondary header log 1 register? and sufep is updated in the ?pcie secondary error capabilities and control register? if r_ma mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 5. error fatal or non-fatal message is generated on pcie as per the severity level of r_ma bit in ?pcie secondary uncorrectable error severity register? if r_ma mask bit is clear in the ?pcie secondary uncorrectable error mask register? or ma_err bit is set in ?pci bridge control and interrupt register? , and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 6. s_serr bit is set in ?pci control and status register? if the r_ma mask bit is clear in ?pcie secondary uncorrectable error mask register? or ma_err bit is set in ?pci bridge control and interrupt register? and the serr_en bit is set 7. ftl_err_dtd/nftl_err_dtd bit is set in the ?pcie device control and status register? 9.2.5.2 master-abort on pci interface for non-posted transaction when the peb383 receives a master-abort on th e pci bus while forwarding a non-posted pcie request, it does the following: 1. returns a completion with unsupported request status on the pcie 2. r_ma bit is set in ?pci secondary status and i/ o limit and base register? 3. r_ma bit is set in ?pcie secondary uncorrectable error status register? 9. error handling > pcie as originating interface 74 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4. header is logged in the ?pcie secondary header log 4 register? and err_ptr is updated in the ?pcie secondary error capabilities and control register? if r_ma mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 5. error fatal or non-fatal message is generated on pcie as per the severity level of r_ma bit in ?pcie secondary uncorrectable error severity register? if r_ma mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_e rr_en bit is set in ?pcie device control and status register? 6. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr enable bit is set in ?pci control and status register? 7. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? 9.2.6 received target-abort on pci interface this section describes the functionality of the pe b383 when a target-abort is received on the pci interface in response to poste d, and non-posted transactions. 9.2.6.1 target abort on a posted transaction when the peb383 receives target-abort on the pci interface for posted requests, it takes the following actions: 1. drops the entire transaction 2. r_ta bit is set in ?pci secondary status and i/o limit and base register? 3. r_ta bit is set in ?pcie secondary uncorrectable error status register? 4. header is logged in the ?pcie secondary header log 1 register? and err_ptr is updated in the ?pcie secondary error capabilities and control register? if r_ta mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 5. error fatal or non-fatal message is generated on pc ie as per the severity level of r_ta bit in the ?pcie secondary uncorrectable error severity register? if r_ta mask bit is clear in the ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in the ?pci control and status register? or ftl_err_en/nftl_err_ en bit is set in the ?pcie device control and status register? 6. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set 7. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? 9.2.6.2 target-abort on pci interface for non-posted transaction when the peb383 receives a target-abort while fo rwarding a pcie non-post ed request to the pci interface, it takes the following actions: 1. returns a completion with completer abort status on the pcie link 2. r_ta bit is set in ?pci secondary status and i/o limit and base register? 3. r_ta bit is set in ?pcie secondary uncorrectable error status register? 9. error handling > pci as originating interface 75 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 4. header is logged in the ?pcie secondary header log 1 register? and err_ptr is updated in the ?pcie secondary error capabilities and control register? if r_ta mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 5. error fatal or non-fatal message is generated on pcie as per the severity level of r_ta bit in ?pcie secondary uncorrectable error severity register? if r_ta mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_er r_en bit is set in ?pcie device control and status register? 6. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set in ?pci control and status register? 7. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? 9.3 pci as originating interface this section describes how the peb383 handles errors for upstream transactions from pci to pcie (see figure 24 ). the bridge supports tlp poisoning as a transm itter to permit proper forwarding of parity errors that occur on the pci interface. figure 24: transaction error forwarding with pci as originating interface table 15 provides the error forwarding requirements for uncorrectable data errors detected by the peb383 when a transaction targets the pcie interface. posted and n on-posted write data received on the secondary pci interface wi th bad parity are forwarded to pcie as poisoned tlps. table 15: error forwarding require ments for received pci errors received pci error forwarded pcie error write with uncorrectable data error write request with poisoned tlp req uest or or del ayed tr ans ac t ion completer peb38x completer pcie (desti nati on i nterf ace) pc i (origi nat ing interface) 9. error handling > pci as originating interface 76 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 16 describes the peb383 behavior on a pci delayed transaction that is forwarded by a bridge to pcie as a memory read request or an i/o read/write request, and the pcie interface returns a completion with unsupported request or comple ter abort completion status for the request. 9.3.1 received pci errors this section describes how the peb383 handles pci errors. 9.3.1.1 uncorrectable data error on a non-posted write transaction pci mode when the peb383 receives non-posted write transac tion that is addressed such that it crosses the bridge, and the bridge detects an uncorrectable data error on its pci interface , it does the following: 1. d_pe bit is set in ?pci secondary status and i/ o limit and ba se register? 2. if s_peresp bit is set in the ?pci bridge control and interrupt register? , then the transaction is discarded and is not forwarded to pcie and the perr# pin is asserted on the pci bus 3. if s_peresp bit is not set in ?pci bridge control a nd interrupt register? , then the data is forwarded to pcie as a poisoned tlp. m_dpe bit is set in ?pci control and status register? if the s_peresp bit is set. the perr# pi n is not asserted on the pci bus 4. uderr bit is set in ?pcie secondary uncorrectable error status register? 5. header is logged in the ?pcie secondary header log 1 register? and err_ptr is updated in the ?pcie secondary error capabilities and control register? if uderr mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 6. error fatal or non-fatal message is generated on pcie as per the severity level of uncorrectable data error bit in ?pcie secondary uncorrectable error severity register? , if uderr mask bit is clear in ?pcie secondary uncorrectab le error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 7. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set 8. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? table 16: error forwarding requirements for pci delayed transaction pcie completion status pci immediate response master-abort mode = 1 pci immediate response master-abort mode = 0 unsupported request (on memory or i/o read) target abort normal completion, return 0xffff_ffff unsupported request (on i/o write) target abort normal completion completer abort targe t abort target abort 9. error handling > pci as originating interface 77 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9.3.1.2 uncorrectable data error on a posted write when the peb383 receives posted write transaction that is addressed such that it crosses the bridge and the bridge detects an uncorrectable data error on its secondary pci interface , it does the following: 1. d_pe bit is set in ?pci secondary status and i/ o limit and ba se register? 2. if s_peresp bit is set in ?pci bridge control a nd interrupt register? , perr# signal is asserted 3. mdp_d bit is set in ?pci secondary status and i/ o limit and base register? if s_peresp bit is set in the ?pci bridge control an d interrupt register? 4. uderr bit is set in ?pcie secondary uncorrectable error status register? 5. header is logged in the ?pcie secondary header log 1 register? and err_ptr is updated in the ?pcie secondary error capabilities and control register? if uderr mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 6. error fatal or non-fatal message is generated on pcie as per the severity level of uderr bit in ?pcie secondary uncorrectable error severity register? if uderr mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_er r_en bit is set in ?pcie device control and status register? 7. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set in ?pci control and status register? 8. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? 9.3.1.3 uncorrectable data error on pci delayed read completions when the peb383 detects perr# asserted by th e initiating pci master while forwarding a non-poisoned read completion from pcie to pci, it does the following: 1. forwards the remainder of completion 2. perr_ad bit is set in ?pcie secondary uncorrectable error status register? 3. header is logged in the ?pcie secondary header log 1 register? and err_ptr is updated in the ?pcie secondary error capabil ities and control register? if, perr_ad mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 4. error fatal or non-fatal message is generated on pcie as per the severity level of perr_ad bit in ?pcie secondary uncorrectable error severity register? , if perr_ad mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_er r_en bit is set in ?pcie device control and status register? 5. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set in ?pci control and status register? 6. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? when the peb383 detects perr# asserted by the in itiating pci master wh ile forwarding a poisoned read completion from pcie to pci, it does the above mentioned actions bu t no error message is generated. 9. error handling > pci as originating interface 78 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9.3.1.4 uncorrectable address error when the peb383 detects an uncorrect able address error, and parity error detection is enabled using the s_peresp bit in ?pci bridge control a nd interrupt register? , the bridge takes the following actions: 1. transaction is terminated with a target abort and discarded 2. d_pe bit is set in ?pci secondary status and i/ o limit and ba se register? independent of s_peresp bit in ?pci bridge control and interrupt register? 3. s_ta bit is set in ?pci secondary status and i/ o limit and base register? 4. uadd_err bit is set in ?pcie secondary uncorrectable error status register? 5. header is logged in the s econdary header log register and err_ptr is updated in the ?pcie secondary error capabilitie s and control register? if uadd_err mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 6. error fatal or non-fatal message is generated on pcie as per th e severity level of uadd_err bit in ?pcie secondary uncorrectable error severity register? if uadd_err mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 7. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set in ?pci control and status register? 8. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? 9.3.1.5 uncorrectable attribute error when the peb383 detects an uncorr ectable attribute error and parity error detection is enabled via the parity error response enable bit in ?pci bridge control and interrupt register? then the bridge takes the following actions: 1. transaction is terminated with a target abort and discarded 2. d_pe bit is set in ?pci secondary status and i/ o limit and ba se register? independent of s_peresp bit in ?pci bridge control and interrupt register? 3. s_ta bit is set in ?pci secondary status and i/ o limit and base register? 4. uatt_err bit is set in ?pcie secondary uncorrectable error status register? 5. header is logged in the s econdary header log register and err_ptr is updated in the ?pcie secondary error capabilitie s and control register? if uatt_err mask bit is clear in ?pcie secondary uncorrectable error mask register? and err_ptr is not valid 6. error fatal or non-fatal message is generated on pcie as per the severity level of uatt_err bit in ?pcie secondary uncorrectable error severity register? if uatt_err mask bit is clear in ?pcie secondary uncorrectable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 9. error handling > timeout errors 79 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 7. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set in ?pci control and status register? 8. ftl_err_dtd/nftl_err_dtd bit is set in ?pcie device control and status register? 9.3.2 unsupported request completion status the peb383 provides two method s for handling a pcie completi on received with unsupported request status in response to a re quest originated by a secondary in terface in pci mode. the bridge?s response to this completion is controlled by the ma_err bit in ?pci bridge control and interrupt register? : ? ma_err bit set ? when ma_err is set the peb3 83 signals a target-abort to the originating master of an upstream read or a non-posted write transaction if the corresponding request on the pcie link results in a completion with unsuppo rted request st atus. the peb383 also sets the s_ta bit in the ?pci secondary status and i/o limit and base register? . ? ma_err bit is cleared ? this is the default pc i compatible mode where an unsupported request error is not considered an error. when a read transaction initiated on the secondary interface results in a completion with unsupported request status, the peb383 returns 0xffff_ffffto the originating master and normally terminates the r ead transaction on the originating interface (by asserting trdy#). when a non-poste d write transaction results in a completion with unsupported request status, the peb383 normally completes the write transaction on the originating bus (by asserting trdy#) and dis cards the write data. in all cases of recei ving unsupported request completion status on pcie in response to a pci request initiated on the secondary interface, the peb383 sets the r_ma in the ?pci control and status register? . 9.3.3 completer abort completion status when the peb383 receives a completion with completer abort status on the pcie link in response to a forwarded non-posted pci transaction, it sets the r_ta bit in the ?pci secondary stat us and i/o limit and base register? . a completer abort response on pcie translates to a delayed transaction target-abort if the secondary interface is in pci mode. the peb383 provides data to the requesting agent up to the point where data was successfully returned from the pcie interface, and then signals target-abort. r_ta is set in ?pci control and status register? when signaling a target-abort to a pci agent. 9.4 timeout errors this section discusses how the peb383 handles pcie and pci timeout errors. 9. error handling > other errors 80 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9.4.1 pcie completion timeout errors the pcie completion timeout function allows re questors to abort a non-posted request if the completion does not arrive within a reasonable period of time. when br idges act as initiators on pcie on behalf of internally generate d requests, and requests forwarded from a secondary interface in pci mode, they act as endpoints for requests that they take owners hip. when the peb383 detects a completion timeout it responds as if a completion with unsupported request status has been received and follows the rules for handling unsuppor ted request completions as described in ?unsupported request completion status? . in addition, the bridge takes the following actions: 1. cto bit is set in ?pcie uncorrectable error status register? 2. error fatal or non-fatal message is generated on pcie as per the severity level of the cto bit in ?pcie uncorrectable error severity register? if cto mask bit is clear in ?pcie correctable error mask register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 3. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and the serr_en bit is set in ?pci control and status register? 9.4.2 pci delayed transaction timeout errors if a delayed transaction timeout is detected the peb383 does the following: 1. error fatal or non-fatal message is generated on pcie as per the severity level of dtdte bit in ?pcie secondary uncorrectable error severity register? , if dtdte mask bit is clear in ?pcie secondary uncorrectable error mask register? or discard_serr bit is set ?pci bridge control and inte rrupt register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 2. no header is logged 3. s_serr bit is set in ?pci control and status register? if an error message (fatal/non-fatal) is generated and serr_en bit is set in ?pci control and status register? 9.5 other errors pci devices can assert serr# when detecting errors that compromi se system integrity. when the peb383 detects serr# on the secondary interface, it does the following: 1. s_serr bit is set in ?pci secondary status and i/ o limit and base register? 2. error fatal or non-fatal message is generated on pcie as per the severity level of serr_ad bit in ?pcie secondary uncorrectable error severity register? if serr_ad mask bit is clear in ?pcie secondary uncorrectable error mask register? or serr_en bit is set in ?pci bridge control and interrupt register? and either serr_en bit is set in ?pci control and status register? or ftl_err_en/nftl_err_en bit is set in ?pcie device control and status register? 3. serr_ad bit is set in ?pcie secondary uncorrectable error status register? 4. sufep field is updated in ?pcie secondary error capabi lities and control register? 5. no header is logged for serr# assertion 9. error handling > error handling tables 81 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 9.6 error handling tables this section contains error handling information in a table format. some of this information may overlap with error informatio n discussed in previous sections of this chapter. table 17: ecrc errors error details primary reporting mechanism ecrc error 1. ?pcie uncorrectable error status register? [ecrc]. 2. ?pci control and status register? [d_pe]. 3. ?pci control and status register? [s_serr] if an error message is generated and [serr_en] bit is set in same register. 4. ?pcie device control and status register? [ftl_err_dtd/nftl_err_dtd]. 5. tlp is dropped. table 18: poisoned tlp errors error details primary reporting mechanism secondary reporti ng mechanism poisoned tlp error 1. ?pcie device control and status register? [cor_err_dtd/ft l_err_dtd]. 2. ?pcie correctable error status register? [anfe] in case of advisory non-fatal condition. 3. ?pcie uncorrectable error status register? [ptlp]. 4. ?pci control and status register? [s_serr] if a fatal error message is sent and [serr_en] bit is set in same register. 5. ?pci control and status register? [d_pe]. 6. ?pci control and status register? [mdp_d] is set if the poisoned tlp is a read completion and [peresp] is set in same register. 1. ?pci secondary status and i/o limit and base register? [mdp_d] if [s_peresp] is set in ?pci bridge control and interrupt register? and pci_perrn pin asserted when forwarding a write request transaction with bad parity to the pci bus. 2. ?pcie secondary uncorrectable error status register? [perr_ad]. 9. error handling > error handling tables 82 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 19: malformed tlp errors error details primary reporting mechanism payload exceeds max_payload_size 1. ?pcie uncorrectable error status register? [mal_tlp] 2. optional err_fatal or err_nonfatal message sent. 3. ?pcie device control and status register? [ftl_err_dtd]/[ nftl_err_dtd]. 4. ?pci control and status register? [s_serr] if error message is generated and [serr_en] is set in same register. 5. tlp discarded. write tlp payload does not match length specified in completion tlp payload does not match length mismatch between td and presence of ecrc address/length combination crosses 4kbyte received intx message with tc > 0 received power management message with tc > 0 received error message with tc > 0 received unlock message with tc > 0 tlp type field uses undefined value illegal byte enables: 1. fbe = 0 when length > 1dw. 2. lbe!= 0 when length = 1dw. 3. lbe = 0 when length > 1dw. 4. non-contiguous byte enables when length = 2dw, and non-quadword aligned address. 5. non-contiguous byte enables when length > 2dw. io request with tc > 0, or attribute > 0 or length > 1dw or lbe > 0 configuration request with tc>0, or attribute > 0 or length >1dw or lbe > 0 violations of rcb rules crs response to non-configuration request 9. error handling > error handling tables 83 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 20: link and flow control errors error details primary reporting mechanisms receiver overflow on header or data 1. ?pcie uncorrectable error status register? [rxo]. 2. ?pcie device control and status register? [ftl_err_dtd]/[ nftl_err_dtd]. 3. optional err_fatal or err_nonfatal message sent. 4. ?pci control and status register? [s_serr] if error message is generated and [serr_en] is set in same register. initial credits advertised are less than minimum 1. ?pcie uncorrectable error status register? [fcpe]. 2. ?pcie device control and status register? [ftl_err_dtd]/[n ftl_err_dtd]. 3. optional err_fatal or err_nonfatal message sent. 4. ?pci control and status register? [s_serr] if error message is generated and [serr_en] is set in same register. received data credits > 2047, or header credits > 127 initial infinite credit advertised, but subsequent updatefc contains non-zero credit value. invalid (that is, non-outstanding) acknack_seq_num in received ack/nak dllp 1. ?pcie uncorrectable error status register? [dlpe]. 2. ?pcie device control and status register? [ftl_err_dtd]/[ nftl_err_dtd]. 3. optional err_fatal or err_nonfatal message sent. 4. ?pci control and status register? [s_serr] if error message is generated and [serr_en] is set same register. tlp ends with edb, but lcrc is not inverted 1. ?pcie correctable error status register? [b_tlp]. 2. ?pcie device control and status register? [cor_err_dtd]. 3. optional err_cor message sent. tlp ends with end, but lcrc is incorrect tlp ends with end, lcrc is correct, but has invalid dllp has invalid crc 1. ?pcie correctable error status register? [b_dllp]. 2. ?pcie device control and status register? [cor_err_dtd]. 3. optional err_cor message sent. replay number rolls over 1. ?pcie correctable error status register? [rn_ro]. 2. ?pcie device control and status register? [cor_err_dtd]. 3. optional err_cor message sent. replay timer expires 1. ?pcie correctable error status register? [rt_to]. 2. ?pcie device control and status register? [cor_err_dtd]. 3. optional err_cor message sent. 9. error handling > error handling tables 84 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 21: uncorrectable data/address errors error details primary reporting mechanism secondary reporting mechanism pcie as originating interface uncorrectable data error on the destination interface (pci) while receiving an immediate response from the completer. 1. ?pci control and status register? [d_pe]. 2. pci_perrn is asserted on the pci interface if the [s_peresp] is set in ?pci bridge control and interrupt register? . 3. ?pcie device control and status register? [ftl_err_dtd]/[nftl_err_dtd]. 4. ?pci control and status register? [s_serr] if an error message (fatal/non-fatal) is generated and [s_serr] is set in same register. 1. ?pci secondary status and i/o limit and base register? [mdp_d] if ?pci bridge control and interrupt register? [s_peresp] is set. 2. ?pcie secondary uncorrectable error status register? [uderr]. pci_perrn asserted on the pci interface while forwarding a non-posted write transaction from pcie. 1. ?pcie device control and status register? [ftl_err_dtd]/[nftl_err_dtd]. 2. ?pci control and status register? [s_serr] if error message is sent and [serr_en] is set in same register. 1. ?pcie secondary uncorrectable error status register? [perr_ad] 2. ?pci secondary status and i/o limit and base register? [mdp_d] if ?pci bridge control and interrupt register? [s_peresp] pci_perrn asserted on the pci interface while forwarding a posted write transaction from pcie. 1. ?pci secondary status and i/o limit and base register? [mdp_d] if ?pci bridge control and interrupt register? [s_peresp] 2. ?pcie secondary uncorrectable error status register? [perr_ad] pci_serrn detected on the pci interface while forwarding transactions from pcie. 1. ?pci secondary status and i/o limit and base register? [s_serr]. 2. ?pcie secondary uncorrectable error status register? [serr_ad]. pci as originating interface uncorrectable data error on a non-posted write transaction pci mode. 1. ?pcie device control and status register? [ftl_err_dtd]/[nftl_err_dtd]. 2. ?pci control and status register? [s_serr] if error message is sent and [serr_en] is set in same register. 1. ?pci secondary status and i/o limit and base register? [d_pe]. 2. ?pcie secondary uncorrectable error status register? [uderr]. uncorrectable data error on a posted write transaction. 1. if s_peresp bit is set in ?pci bridge control and interrupt register? , perr# signal is asserted. 2. ?pcie device control and status register? [ftl_err_dtd]/[nftl_err_dtd]. 3. ?pci control and status register? [s_serr] if error message is sent and [serr_en] is set in same register. 1. ?pci secondary status and i/o limit and base register? [d_pe]. 2. ?pci secondary status and i/o limit and base register? [mdp_d] if [s_peresp] bit is set in the ?pci bridge control and interrupt register? . 3. ?pcie secondary uncorrectable error status register? [uderr]. 9. error handling > error handling tables 85 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required uncorrectable data error on pci delayed read completions. 1. ?pcie device control and status register? [ftl_err_dtd]/[nftl_err_dtd]. 2. ?pci control and status register? [s_serr] if error message is sent and [serr_en] is set in same register. 1. ?pcie secondary uncorrectable error status register? [perr_ad] uncorrectable address error 1. ?pci secondary status and i/o limit and base register? [d_pe]. 2. ?pci secondary status and i/o limit and base register? [s_ta]. 3. ?pcie secondary uncorrectable error status register? [uadd_err]. table 22: received master/target abort error error details primary reporting mechanism secondary reporti ng mechanism master-abort on the pci bus while forwarding a posted write transaction from pcie 1. ?pci control and status register? [s_serr] if r_ma mask bit is clear in ?pcie secondary uncorrectable error mask register? or ma_err bit is set in ?pci bridge control and interrupt register? and ?pci control and status register? [serr_en] is set. 2. ?pcie device control and status register? [ftl_err_dtd]/[n ftl_err_dtd]. 1. ?pci secondary status and i/o limit and base register? [r_ma]. 2. ?pcie secondary uncorrectable error status register? [r_ma]. master-abort on the pci bus while forwarding a non-posted write transaction from pcie 1. ?pcie device control and status register? [ftl_err_dtd]/[n ftl_err_dtd]. 2. ?pci control and status register? [s_serr] if error message is sent and [serr_en] is set in same register. target-abort on the pci bus while forwarding a posted transaction from pcie 1. ?pcie device control and status register? [ftl_err_dtd]/ [nftl_err_dtd]. 2. ?pci control and status register? [s_serr] if error message is sent and [serr_en] is set in same register. 1. ?pci secondary status and i/o limit and base register? [r_ta]. 2. ?pcie secondary uncorrectable error status register? [r_ta]. target-abort on the pci bus while forwarding a non-posted transaction from pcie table 21: uncorrectable data/address errors (continued) error details primary reporting mechanism secondary reporting mechanism 9. error handling > error handling tables 86 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 23: completion errors error details primary report ing mechanism secondary reporti ng mechanism completion received with unsupported request in response to a request originated by a secondary interface in pci mode. 1. ?pci control and status register? [r_ma]. 1. ?pci secondary status and i/o limit and base register? [s_ta] is set if [ma_err] bit in ?pci bridge control and interrupt register? is set. completion received with completer abort status on the pcie link in response to a forwarded non-posted pci transaction. 1. ?pci control and status register? [r_ta]. 1. ?pci secondary status and i/o limit and base register? [s_ta]. received unexpected completion error 1. ?pcie uncorrectable error status register? [uxc] if not masked. 2. ?pcie device control and status register? [cor_err_dtd] if anfe. n/a completion timeout error 1. ?pcie uncorrectable error status register? [cto] if not masked. 2. ?pcie device control and status register? [cor_err_dtd] if anfe. n/a table 24: request errors error details primary report ing mechanism secondary reporti ng mechanism received vendor message (type 0). 1. ?pcie uncorrectable error status register? [ur] if not masked. 2. ?pcie device control and status register? [uns_req_dtd]. 3. ?pcie device control and status register? [cor_err_dtd] if anfe. n/a non-configuration or message received while in d1, d2 or d3 hot. configuration type 0 access with a non-zero function. 87 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10. reset and clocking topics discussed include the following: ? ?reset? ? ?clocking? 10.1 reset the peb383 inputs resets from upstream devices , and drives reset to downstream devices. pcie_perstn is the reset input to the bridge, and is normally connected to a power-on reset controller at the system level. the peb383 drives re set onto the pci bus using pci_rstn (see table 25 ). table 25: reset summary reset level pci definition trigger eeprom load peb383 actions 0 cold reset warm reset pcie_perstn yes ? initialize all registers to known state (including sticky) ? drive and release pci_rstn 1 ms after pcie_perstn is released 1 hot reset reset message or dl_down state yes ? initialize all registers to known state (except sticky ? drive and release pci_rstn 1 ms after peb383 is completed reset 2 pci bus reset set reset bit in csr through configuration cycle no ? hold pci_rstn low for 1 ms, or until bit is cleared by software, which ever is longer ? drain traffic ? drop request tlps ? enumerate bus mode and clock speed (if clock master) ? do not initialize csr 10. reset and clocking > reset 88 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10.1.1 pcie link reset pcie resets flow from upstream devices. the pcie in terface is a slave to resets through a system-level power-on reset controller connect ed to pcie_perstn, or through inband messages from the root complex. after release of reset the external eeprom is loaded. during the loading process, configuration requests will receive a ?configur ation request retry stat us? completion status. 10.1.1.1 cold reset ? level 0 a cold reset is applied after power up. this is a trad itional power-on reset that is generally driven at the system level by a power-on reset controller. after release of pcie_perstn, all of peb383?s registers are in their power-on reset state, including sticky bi ts. clock (pcie_refclk_n /p) and power must be valid prior to the release of pcie_perstn. the ti ming diagram for a cold reset is displayed in figure 25 , while its values are listed in table 26 . figure 25: reset timing 10.1.1.2 warm reset ? level 0 a warm reset occurs without cycl ing power. this is achieved by bringing pcie_perstn low for the minimum specified time, t perst . after release of pcie_perstn, all of peb383?s registers are in there power-on reset state, including sticky bits. table 26: reset timing parameter value min./max. description t pvperl 10 ms minimum power valid to release of reset t perst-clk 10 ms minimum clock valid to releases of reset t perst 1 ms minimum minimum pulse for reset (warm reset) t fail 1 ms maximum time to assert reset after power is not valid tpvperl pci e_pe rstn clock valid pw r valid tperst-clk tpers t tfail 10. reset and clocking > reset 89 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10.1.1.3 hot reset ? level 1 a hot reset is triggered by an in-band message fr om the root complex over the pcie link. after application of hot reset, all registers are in their po wer-on reset state, except sticky bits which maintain their pre-reset values in order to aid in system diagnostics. a hot reset is also be initiated during a dl_down condition. dl_down means that the peb383 has lost communications at the physical or data link layer with the upstream device. 10.1.2 pci bus reset the peb383 drives reset on the pci bus using pci_ rstn. there are four cond itions that cause the bridge to drive reset onto the pci bus: 1. assertion of pcie_per stn (cold/wa rm reset) 2. receipt of a hot reset message on the pcie link (hot reset) 3. pcie link going into a dl_down state (hot reset) 4. setting the pci bus reset bit, s_reset, in the ?pci bridge control an d interrupt register? (level 2). software must ensure there are no requests pending in the device buffers befo re setting the pci reset bit. if software fails to do so, the peb383 drains its buffers as follows. ? drops all upstream requests and as sociated completions pending in the pci core buffers. requests pending in pcie core buffers, howe ver, are transmitted normally. ? drops all downstream requests and returns the cr edits, and also returns completions with ur completion status for non-posted requests. 10. reset and clocking > clocking 90 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10.2 clocking this section discusses clocking information for the peb383?s pcie and pci interfaces. 10.2.1 pcie clocking the pcie clocking is shown in figure 26 . the 100-mhz reference clock, pcie_refclk_n/p, drives a x(5/4) pll to create a 125-mhz clock. the 125-mh z clock is further multiplied to create the tx parallel to serial conversion, a nd clocking out the tx pi ns, pcie_txd_n/p (the r eceive data is clocked into the peb383 with the recovere d clock. the elastic buffer operat es on the recovered byte clock (from k28.5) and the intern al generated 125-mhz clock. the two clocks can vary by twice the ppm tolerance of the reference clock to lerance on any one device (300ppm). buffer overflow is prevented by discarding skip characters. figure 26: pcie clocking pcs phy pcs pci e_r efcl k_ p pci e_r efcl k_ n pll x(5/4) 8b10b encode parallel to serial t x di ff er en ti a l dr ive r pcie_txd_p pcie_txd_n 100 mhz 125 mh z pll x2 0 2.5 ghz r x d iff er en tia l receiver pci e_ rxd _p pci e_ rxd _n c loc k re co ve ry data recovery serial to parall el elastic buffer recovered 2.5 ghz 10b8b decode k28.5 16 20 20 16 1 25 mhz (t o pci e co re ) 10. reset and clocking > clocking 91 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10.2.2 pci clocking the pci clocking for the peb383 is shown in figure 27 . the peb383 supports clock master and slave mode, and is configured by the pcb design. the bridge drives up to four external clocks, pci_clko[3:0], which are individually enabled through the ?clock out enable function and debug register? . pci_clko[4] can be used for external clock compensation. figure 27: pci clocking 10.2.2.1 master mode clocking master mode clocking is provided by the peb383 . pci_clko[4:0] is gene rated from pcie_refclk and a programmable pll. the decoder sets the divide r ratios for programmable pll as a function of pci_m66en, and the ?pci miscellaneous clock straps register? . pci_m66en selects 66 mhz when high, and 33 mhz when low. the ?pci miscellaneous cl ock straps register? allows this pin to be overwritten, and one of the following speeds used: 25, 33, 50, and 66 mhz. prior to the configuration of the pci bus speed, the pci clock is in bypass mode, which generates a 25-mhz clock on the pci bus. afte r the release of reset, the pll locks to a new frequency based on the value of the pci_m66en signal (see table 27 ). table 27: pci clocking pci bus rate pci_m66en signal 25 mhz requires software configuration a 33 mhz 0 50 mhz requires software configuration 66 mhz 1 pci e_r efclk_p pci e_r efclk_n pci _c lko[4 :0 ] pci_m66en pci_clk decoder logic in te rn al c lk clk tree 10 0 m hz programma ble pll pw ru p_p ll _b ypass 10. reset and clocking > clocking 92 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required pci_clko[3:0] are connected to pci devices, wh ile pci_clko[4] is connected to the pci_clk signal. the track length of the clock nets should be matched in length. 10.2.2.2 slave mode clocking in slave clocking, pci_clko[0] is disabled through the ?clock out enable function and debug register? , and an external clock source drives the pe b383 (using pci_clk) and the pci devices. a. this setting is based on the value of cs_mode in the ?pci miscellaneous clock straps register? . 11. power management > overview 93 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11. power management topics discussed include the following: ? ?overview? ? ?power management capabilities? ? ?power states? 11.1 overview the peb383 provides basic power management supp ort to its pci bus and pcie link. pci power management states are mapped to specific pcie li nk states. the bridge also supports active state power management (aspm), where the device enters into power saving state and initiates exit when needed. the peb383 transmits power management messages during power management events. the power management (pm) module connects with the physical layer sub block to transition the link state into low-power states when it recei ves a power state change request from a upstream component, or when an internal ev ent forces the link state entry into low-power states in aspm. pcie link states are not visible direct ly to legacy bus driver software but are derived from the power management state of the components residing on those links. power saving increases as link state transitions from l0 through l3. 11.1.1 features ? compliant with the pci bus power management interf ace specification (revision 1.2) ? supports the following pci device power states: ?d0 ? d3 hot ?d3 cold ? supports the following pcie link power states: ?l0 ?l0s ?l1 ? l2/3 ready ?l3 11. power management > power management capabilities 94 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.1.2 unsupported features ? pci power states: d1 and d2 ? pcie link states: l2 ? pci bus states ? wake# to beacon ?pme in d3 cold ? auxiliary power 11.2 power management capabilities the peb383 supports software driven d-state power management: d0, d3hot, and d3cold. it supports l0s state in ac tive state power manageme nt method; l0s entry should be enabled through configuration of aspm_ctl in the ?pcie link control register? . it also support l1, l2/l3 ready and l3 pcie power saving link states. since the peb383 does not support auxiliary power it does not support power management events in the d3cold state. the peb383 enters into link power management states in response to the software driven d-state. the power management related registers reside at ?pci power management capability register? and ?pci power management cont rol and status register? . 11.3 power states this section discusses the peb383?s support of pci and pcie power states. 11.3.1 aspm active state power management, or aspm, enables power savings even when the peb383 is in the d0 state. after a period of idle link time, the aspm fu nction engages the physical layer protocol that places idle link in the power savi ng state. once in the lower power state, transitions to the fully operative l0 state can be triggered by transactions from the pcie or pci interface. the l0/l1 entry capability of the peb383 is determined by the root complex reading the peb383 configuration space ?pcie link capabili ties register? . the root complex can enable entry into this state through configuration. l0s is not applicable to the pci-pm compatible power management. all main power supplies, component reference clocks, and component internal plls, must be active at all time during l0s. dllp and tlp transmission through the peb383 in l0s is prohibited. the peb383?s pcie transmit module can be in l0s stat e while the transmit module of the other device on the pcie link is in the l0 state . in the peb383, l0s entry is disabled by default. when l0s entry is enabled and the peb383 transmit module is in idle st ate for more then 6 micro seconds ? that is, there is no transmission of packets for 6 micro seconds ? the peb383 transmit module enters the l0s state. the bridge initiates exit from the l0s state when it has pending tlps or dllps for transmission. the aspm function of the peb383 does support l1 entry. 11. power management > power states 95 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.3.2 l0 state this is the normal operational mode. 11.3.3 l0s state a low resume latency, energy-saving standby state. l0s support is required for aspm. it is not applicable to pci-pm compatible power management. 11.3.4 l1 state l1 is a high latency and low-power standby stat e. it is required for pci-pm compatible power management. the peb383 does support l1 entry in aspm. the l1 may be entered whenever the bridge is programmed to a d3 stat e. l1 is also entered by aspm wh en there is no pending packet to transmit for 10us. tlp and dllp communication over the link is prohibited when the peb383 is in the l1 state. l1 exit can be initiated by the peb383 or an upstream device. 11.3.5 l2/l3 ready the l2/l3 ready state is a staging point for the l2 or l3 states. the process is initiated after the pm module software transitions the peb383 into the d3 state and requests power management software to initiate the removal of power and clocks. after the pcie link enters the l2/l3 ready state the peb383 is ready for power removal. tlp and dllp communi cation over link cannot occur while the peb383 is in this state. it is also possible to remove po wer without first placing the peb383 in the d3hot state. system software causes the root complex to broa dcast the pme_turn_off message in preparation for removing the main power source, a nd the peb383 responds in order to complete entry into the l2/l3 ready state. 11.3.6 l3 state when the peb383 is in l2/l3 ready state, the re moval of main power and clocks places the device into the l3 state. the peb383 does not support auxi liary power, therefore l2 power management state is not supported. 11.3.7 ldn state this is a pcie link down pseudo state prior to l0. 11. power management > power states 96 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.3.8 link state summary the link states are summarized in table 28 . the link state diagram is shown in figure 28 . figure 28: pcie link power management states table 28: pcie link states l state description software directed pm aspm 100-mhz reference power internal pll l0 fully active link yes (d0) yes (d0) on on on l0s standby state no yes (d0) on on on l1 low-power standby yes (d3 hot ) yes on on on l2/l3 ready stagging point for power removal yesno ononon l3 off n/a n/a off off off l0s l1 l0 l2/l3 ready l3 ldn return to l0 through ltssm l0s return tp l0 through ltssm recovery state l2/l3 ready - psudo-state to prepare component for loss of power and ref clock link reinitialization through ltssm detect state linkdown - transient pseudo- state to get back to l0 - entered through fundament al reset, hotreset, or transmissio n by the upstream component this arc indicates the case where the platform does not use vaux 11. power management > power states 97 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.3.9 device power states the peb383 supports the pcie pci-pm d0, d3hot, and d3cold (no auxiliary power) device power management states. the bridge does not support the d1 and d2 power management states. 11.3.10 d0 state d0 is divided into two distinct sub states: the uni nitialized sub-state and th e active sub-state. when power is initially applied to the peb383, it enters the d0_uninitializ ed state. the br idge enters the d0_active state when eith er of the following is set by system software: ? memory space enable ? i/o space enable ? bus master enable 11.3.11 d3 hot state a device that is in the d3hot state must be able to respond to configuration accesses so that it can be moved to the d0_uninitialized state by software through configuration. once in the d3hot state, the device can later be transitioned into the d3cold st ate by removing power from the device. d3hot is a useful state for reducing power c onsumption by idle components in an otherwise running system. once the peb383 is programmed to the d3hot state, it initiates l1 entry process. the no_soft_rst bit in the ?pci power management control and status register? is set to 1 in the peb383 when software programs the bridge back to the d0 state. l1 exit can be initiated by the peb383 or an upstream device. 11.3.12 d3 cold state the peb383 transitions to the d3cold state when its power is removed. re -applying power causes the device to transition from the d3cold state into the d0_uninitialized state. the d3cold state assumes that all previous contexts are lost , so software must save the necessa ry context while th e device is still in the d3hot state. a power-on sequence with its as sociated cold reset transi tions the peb383 from the d3cold state to the d0 uninitialized state. software must perform a full initialization of the peb383 in order to restore the function to its d0 active state. 11. power management > power states 98 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.3.13 d state transitions the device power state transitions are shown in figure 29 . software is responsi ble for controlling the state diagram throu gh pwr_st in the ?pci power management control and status register? . figure 29: d state transitions 11.3.14 power management event power management events are generated by the peb 383 as a means of requesting a pm state change. the peb383 sends a pm_pme message to the root complex during a power management event. the bridge does not support a wake-up function through beacon and wake#. it does not support pme generation from the d3cold state since the peb383 does not support auxiliary power. a pm_pme message are posted tlp packets that are always routed in the direction of the root complex. to send a pm_pme message on its upstream link, the peb383 must transition the link to the l0 state if the link is not already in the l0 state. the pci_pmen pin is sampled ev ery 100 microseconds for pm_pme message generation. d0 uninitialized d0 active power on reset d3 hot d3 cold power removed power applie d hot reset 11. power management > power states 99 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.3.15 power state summary the state summary is shown in table 29 . table 29: power management state summary peb383 state link state upstream state pci bus description d0 l0 d0 operational fully operational d0 l0s d0 operational pcie link in standby d0 l1 d0 operational pcie link in l1 d3 hot l0 d3 hot -d0 pme only a a. the peb383 drives pci_clko[4:0], does not a ssert pci_rstn, responds to pci_pmen, does not participate in bus transactions. peb383 sending pme message when in d3hot or when injecting a pme_to_ack tlp when peb383 transitions between l1 and l2/l3 ready. d3 hot l1 d3 hot -d0 pme only power saving mode, or waiting to transition to l2/l3 ready d3 hot l2/l3 ready d3 hot -d0 not operational ready to remove power, will not respond to pme d3 cold n/a d3 cold -d0 n/a power removed 11. power management > power saving modes 100 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11.4 power saving modes the peb383 provides several low power modes of operation, as described in table 30 . mode1 is fully operational, no power saving modes used. mode2 has aspm disabled, no power saving modes used. mode3 has aspm l0s enabled, link power is saved. mode4 has aspm l1 enabled, additional link power is saved, and internal core logic clock is gated for additional power savings mode5 is d3_hot, link is in l1, and internal clock is gated mode6 is d3_hot, link in l1, internal clock is gated, and external pci_clk[3:0] is gated. table 30: power saving modes input conditions power saving activities mode state aspm a a. aspm enabled via ?aspm_ctl? bit of ?pcie link control register? pci_clk[3:0] gate enable b b. pci_clk[3:0] gating enabled via ?pcge? bit ?pci miscellaneous clock straps register? traffic pci_clk[3:0] link state internal clock 1do x x active on l0 on 2 do none x idle on l0 on 3 do l0s x idle on l0s on 4 do l1 x idle on l1 gated 5 d3_hot x no idle on l1 gated 6 d3_hot x yes idle gated l1 gated 101 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 12. serial eeprom topics discussed include the following: ? ?overview? ? ?system diagram? ? ?eeprom image? ? ?functional timing? 12.1 overview the peb383 uses an internal serial eeprom contro ller to configure its configuration space register (csr) block with the values stored in an external serial eeprom . the controller is compatible with eeprom devices that use the seri al peripheral interface, such as the atmel at25010a, at25020a, at25040a, at25080a, at25160a, at25320a, and at25640a. the primary purpose of the eeprom controller is to modify some of the default values of the read-only and read/write registers in the pe b383?s csr space (for mo re information, see ?register descriptions? ). after reset is de-asserted, the controller in itiates the read instructions to the external eeprom and reads its cont ents. if an eeprom is present the controller writes its data into the peb383?s register space depending on the offs et address provided in the eeprom location. the eeprom controller can write data into an external eeprom using the ?eeprom control register? . it supports 9-bit and 16-bit addressing modes to read and write the external eeprom. 12. serial eeprom > system diagram 102 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 12.2 system diagram figure 30 shows the eeprom controller interfaci ng an external eeprom to the peb383 configuration space. figure 30: eeprom interface the peb383 internal clock block generates an eepro m clock of 7.8 mhz to supply to the external eeprom. this clock is derived from th e pcie clock of frequency 125 mhz. the first two locations in the eeprom ? byte ad dress 0x0000 and 0x0001 ? contain the identification code. the next two locations contai n the byte count, which indicates the number of bytes to be read from the eeprom locations. after this, the next two locations of the eeprom contain the csr address, and the byte enables to in dicate the valid byte locations to be loaded from the eeprom. the next four locations after this contain the 4 bytes of data to be loaded into configuration space. thereafter, the data structure is maintained in the eeprom, per register, as 2 bytes of address and byte enables followed by 4 bytes of data. therefore, th e value in the third and fourth locations of the eeprom, which is the byte count, should always be a multiple of 6 since 6 bytes of information (which includes address, byte enables, and da ta) is required to program one csr register. table 31 describes the data structure to be maintained by the external eeprom. after the reset is de-asserted, the eeprom controller initiates a read of the first two locations of the external eeprom to get the identification code. the identification code must be 0x28ab. initially, it initiates a read transaction with 9- bit address, and reads the identifi cation code. if the identification code results in a wrong value ? that is, other than ab ove value ? then it initiates another read transaction with a 16-bit address to read the id entification code. if th e value read is other than the id entification code, then it determines that an eeprom is not present. it then sets this inform ation in add_width of the ?eeprom control register? , and aborts the programming of the configuration space by signaling the completion of the loading. if the byte count value is programmed to 0 or greater and is a non-multiple of 6, then the eeprom controller rounds up this value to the ne xt nearest value (which is a multiple of 6). the eeprom controller then pr oceeds to program the csr as per this new byte count value. if a blank eeprom is used, the add_width bits in the ?eeprom control register? must be written with the correct bit pattern for the type of eeprom before accessing the eeprom. configuration space register eeprom controller eeprom device peb38x sr_clk sr_csn sr_dout sr_din 12. serial eeprom > system diagram 103 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required if the identification code obtained through the fi rst read is a correct value, then the eeprom controller determines that the eeprom supports 9- bit addressing. the contro ller then initiates one more read transaction to read th e third and fourth locations of th e eeprom, where the value of the total number of bytes to be read (byte count) is lo cated. thereafter, it contin uously reads all the bytes and programs the csr registers depending on the address provided in th e eeprom location. the peb383 has now determined the eeprom controller supports 9-bit addressing (it uses this mode for writes as well). if the identification code read after first read is a wrong value, and af ter the second read is a correct value, then it initiates one more read transaction to get the value of total number of bytes to be read (byte count). thereafter it reads all the bytes fr om the eeprom locations and programs the csr registers according to the addresses given in th e eeprom locations. the pe b383 has now determined the eeprom controller supports 16-bit addressi ng (it uses this mode for writes as well). in both cases just discussed, the controller updates the ?eeprom control register? with the address width of the eeprom detected and si gnals the completion of the loading to the csr block. during the process of programming the csr by the eeprom , any configuration transactions on the pcie interface that are initiated by the root complex are completed with crrs completions (configuration request retry status completions). all other transa ctions are completed with ur completions. the root complex can access th e external eeprom through the eeprom controller; that is, eeprom locations can be written and read by the root complex. the root complex initiates configuration write trans actions to program the ?eeprom control register? using a write command. the eeprom controller initiate s a wren (write enable) instru ction first, followed by a write instruction. the controller sets the busy bit in the register when it initiates a write instruction to the external eeprom. it obtains the status of the wr ite cycle from the external eeprom by initiating rdsr (read status register) instruction to it afte r every write instruction. if the external eeprom finishes the write operation it would return the status in the form of busy bit as 1'b0. this information from the external eeprom is updated in the ?eeprom control register? ; that is, this bit would reset once the external eeprom completes the write operat ion. therefore, software should poll this bit to get busy status before initiating another transa ction to the serial eeprom. as a result, this bit should indicate 1'b0 before initiat ing any other instruction to the external eeprom. software should ensure that the cmd_vld bit in this register is high in order to trigger the eeprom controller to initiate read/write instructions. if a configuration write is initiated to overwrite the command in the ?eeprom control register? during the busy state, the eeprom controller will ignore the command. to read the eeprom location, the root complex in itiates a configuration write transaction to the ?eeprom control register? with the read command; this prompts the eeprom to initiate a read instruction to the external eeprom. when the pcie reset signal is asserted, all the csr re gister values are set to their default values. when this reset is de-asserted, the eeprom controller starts the eeprom loading process in order to re-program its csr registers. the eeprom controller does no t support the wrdi (write disable) and wrsr (write status register) instructions. 12. serial eeprom > eeprom image 104 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 12.3 eeprom image the data structure to be maintained in the extern al eeprom for successful operation of the eeprom controller is shown in table 31 . note that the m and n in the description column indicate the register number: they can point to any regi ster in the entire csr space. the byte enable[3:0] is active high; a 1 enables th e byte. for example, a byte enable of 0b0001 would enable the low order byte, bits[7:0] of the dword. table 31: eeprom image serial eeprom location description value 0000h identification code [7:0] 0xab 0001h identification code [15:8] 0x28 0002h byte count [7:0] any value 0003h byte count [15:8] any value, but total value of byte count[15:0] should be multiple of 6 0004h csr register m address [7:0] any number 0005h csr register m byte enable [3:0], csr register m address [11:8] any number 0006h csr register m data [7:0] any number 0007h csr register m data [15:8] any number 0008h csr register m data [23:16] any number 0009h csr register m data [31:24] any number 000ah csr register n address [7:0] any number 000bh csr register n byte enable [3:0], csr register n address [11:8] any number 000ch csr register n data [7:0] any number 000dh csr register n data [15:8] any number 000eh csr register n data [23:16] any number 000fh csr register n data [31:24] any number ... ... ... fffah csr register r address [7:0] any number fffbh csr register r byte enable [3:0], csr register r address [11:8] any number fffch csr register r data [7:0] any number fffdh csr register r data [15:8] any number 12. serial eeprom > functional timing 105 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 12.4 functional timing the eeprom controller outputs the data on the sr_din signal on every negative edge of the sr_clk clock. the external eeprom samples this output on every positive edge of sr_clk. similarly, the external eeprom ou tputs the data on sr_dout on every negative edge of sr_clk, while the controller samples it on every positive edge of the clock. for read or write instructions in support of addr esses greater than 0xffh (i n 9-bit addressing mode), the 8th bit of the address is transmitted in place of the third bit of the opcode of that instruction; thus, the address phase consists of 8 clock cycles. the timing for different instructions of the eeprom controller are provided in the following figures. figure 31: 9-bit eeprom read timing fffeh csr register r data [23:16] any number ffffh csr register r data [31:24] any number table 31: eeprom image (continued) serial eeprom location description value sr_csn sr_clk sr_din sr_dout opcode address data high-z sr_csn sr_clk sr_clk sr_din sr_din sr_dout sr_dout opcode address data high-z 12. serial eeprom > functional timing 106 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 32: 16-bit eeprom read timing figure 33: 9-bit eeprom write timing sr_csn opcode address data sr_clk sr_din sr_dout high - z sr_csn opcode address data sr_clk sr_din sr_dout high - z sr_csn sr_clk opcode address data sr_dout high-z sr_din sr_csn sr_clk opcode address data sr_dout high-z sr_din 12. serial eeprom > functional timing 107 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 34: 16-bit eeprom write timing figure 35: eeprom wren instruction timing figure 36: eeprom rdsr instruction timing sr_csn sr_clk opcode address data sr_dout high-z sr_din sr_csn sr_clk opcode address data sr_dout high-z sr_dout high-z sr_din sr_csn sr_clk sr_din sr_dout high-z sr_csn sr_clk sr_din sr_dout high-z sr_clk sr_din high-z sr_csn sr_dout opcode data sr_clk sr_din high-z sr_csn sr_dout opcode data note: rdsr means read status register instruction. 12. serial eeprom > functional timing 108 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 109 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 13. jtag topics discussed include the following: ? ?overview? ? ?tap controller initialization? ? ?instruction register? ? ?bypass register? ? ?jtag device id register? ? ?jtag register access? ? ?dedicated test pins? ? ?accessing serdes tap controller? 13.1 overview the jtag interface is compliant with ieee 1149.6 b oundary scan testing of advanced digital networks , as well as ieee 1149.1 standard test access port and boundary scan architecture standards. there are five standard pins associated with the interface (jtag_tms, jtag_tck, jtag_tdi, jtag_tdo, and jtag_trstn) that allow full control of the in ternal tap (test access port) controller. the jtag interface has the following features: ? contains a 5-pin test access port (tap) contro ller, with support for the following registers ? instruction register (ir) ? boundary scan register ?bypass register ? device id register ? user test data register (dr) ? supports debug access of the peb383?s configuration registers ? during mission mode or not ? bus arbitration with configuration cycles ? supports the following instruction opcodes ? sample/preload ?extest ? extest_pulse (1149.6) ? extest_train (1149.6) 13. jtag > tap controller initialization 110 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? bypass ? idcode ?clamp ? user data select 13.2 tap controller initialization after power-up of the peb383, the tap controller must be put into its test-logic-reset state to disable the jtag logic and allow the brid ge to function normally. this can be completed by driving the jtag_tms signal high and pulsing the jtag_tck si gnal five or more time s, or by asserting the jtag_trstn signal. 13.3 instruction register the peb383 uses an instru ction register to control the operatio n of the jtag logic. bit combinations that are not equivalent to any instruction are equivalent to th e bypass instruction. 13.4 bypass register this register is a 1-bit shift regi ster that provides a single bit s can path between the jtag_tdi input and the jtag_tdo output. this abbreviated scan pa th is selected by the bypass instruction code, and is used to shorten the overall scan ring length during board-level testing when the peb383 is not involved. 13.5 jtag device id register the jtag device identifi cation number for the pe b383 is as follows: ? version [31:28] ? 0000 ? part number [27:12] ? 0000_0011_1000_0011 ? manufacturer identity [11:1] ? 000_1011_0011 ? mandatary lsb [0] ? 1 13. jtag > jtag register access 111 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 13.6 jtag register access the jtag interface can be used fo r debug purposes in order to perform read and write access of the peb383?s configuration registers. it also can perform read accesses on the performance registers without impacting active transactions. a user-defined command enables the read and write cap abilities of the jtag in terface. this is in the user test data register (dr) set in the peb383. 13.6.1 register access from jtag the format for access the peb383?s dr register usin g jtag is shown in the following figures. the same dr register is used for read and write access. figure 37: read/write access from jtag ? serial data in figure 38: observe from jtag ? serial data out 13.6.2 write access to regist ers from the jtag interface complete the following steps to write to a device register through the jtag interface: 1. move to the tap controller ?shift-ir? state and program the instruction register with the instruction of the dr by wr iting into instruction regist er bits with 0xffff_ffff_ffff_fffd. 2. move to the ?shift-dr? state a nd shift the data[31:0], r/w = 1 and the address[9:0] serially in the tdi pin. to prevent corruption of unused bits, the full dr bits have to be written as follows (see also figure 37 ): ? dr[66:62] = 5b?0 ? dr[61:52] = addr[9:0] 1 ? dr[51] = r/w ? dr[50:19] = data[31:0] ? dr[18:17] = 2b?0 tip for more information about the test data register, see test technology standards committee: ieee computer society, ieee standard test access port and boundary-scan architecture , ieee std. 1149.1-1990, 1149.1a-1993, october, 1993., section 8.3. 1. note that the address here is the dword address, not the by te address. take the byte address and remove the 2 lsbs, >>2. jtag_tdi jtag_tdo address [9:0] r/w ready error data [31:0] rsvd [16:0] reserved [66:62] jtag_tdi jtag_tdo data [31:0] error reserved [66:34] ready 13. jtag > jtag register access 112 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? dr[16:0] = 17b?0 note : bit 0 is shifted first, and bit 66 is shifted last. 3. move to the ?run-test idle? state and loop in this state for a minimum of 20 tck cycles. 4. move to the ?shift-dr? state again and shift the ready bit and error bit through jtag_tdo (see figure 38 ). ? first bit shifted out is the ready bit. ? second bit shifted out is the error bit. ? verify that the ready bit is at logic high and the error bit is at logic low. note : to prevent corruption, the dr register must be loaded as descri bed in step 2 while shifting out through jtag_tdo for observation. 5. go back to step 2 to perform another write. 13.6.3 read access to regist ers from jtag interface complete the following steps to read a de vice register through the jtag interface: 1. move to the tap controller ?s hift-ir? state and program the in struction register with irac instruction by writing into instruction regi ster bits with 0xffff_ffff_ffff_fffd. this step is optional if the instruction register is already programmed during the write cycle. 2. move to the ?shift-dr? state and shift the r/w = 0 and the address[9: 0] serially in the tdi pin. to prevent corruption of unused bits, the full dr bits have to be written as follows (see also figure 37 ): ? dr[66:62] = 5b?0 ? dr[61:52] = addr[9:0] 1 ? dr[51] = r/w ? dr[50:19] = data[31:0] ? dr[18:17] = 2b?0 ? dr[16:0] = 17b?0 note : bit 0 is shifted first, and bit 66 is shifted last. 3. move to the ?run-test idle? state and loop in this state for a minimum of 20 tck cycles. 4. move to the ?shift-dr? state ag ain and shift the ready bit, error bit, and data[31: 0] out through jtag_tdo (see figure 38 ). ? first bit shifted out is the ready bit. ? second bit shifted out is the error bit. 1. note that the address here is the dword address, not the by te address. take the byte address and remove the 2 lsbs, >>2. 13. jtag > dedicated test pins 113 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? verify that the ready bit is at logic high and the error bit is at logic low. note : to prevent corruption, the dr register must be loaded as descri bed in step 2 while shifting out through jtag_tdo for observation. 5. go back to step 2 to perform another read. 13.7 dedicated test pins the following pins are dedicated to test: ? test_on (scan shift enable; this signal is tied low for normal operation) ? test_bce (boundary scan complian ce enable; this signal is tied low for normal operation) ? this pin configures the serdes built-in tap controller and the peb383 top-level tap controller into a daisy chain. test_bce uses a pad with a built-in pull-up. when test_ bce is low, the bridge?s jtag pins access only the top-le vel tap controller. when test_ bce is high, the daisy chain mode is selected (see figure 39 ). 13.8 accessing serdes tap controller the serdes has an internal tap controller that us es idcode instruction for the ip identi fication and crsel instruction for writing and re ading registers in the ip. to access the serdes tap controller through jtag pins, jtag_tdi pin of serdes is connected to the jtag_tdi pin and the tdo of serdes is connected to the jtag_tdi of the peb3 83?s top-level tap contro ller through a mux with jtag_bce pin as selector. figure 39 shows the connections between th e bridge?s tap controller and the serdes tap controller. figure 39: pcie serdes connections serdes tap controller tdi tdo tdo tdi 0 1 z bce lv tap controller tdi tdo 13. jtag > accessing serdes tap controller 114 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 115 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14. register descriptions topics discussed include the following: ? ?overview? ? ?pci configuration space? ? ?register map? ? ?upstream non-transparent ad dress remapping registers? ? ?pci capability registers? ? ?pcie capability registers? ? ?downstream non-transparent address remapping registers? ? ?advanced error reporting capability registers? ? ?pcie and serdes control and status registers? 14.1 overview the following terms describe the peb383?s regist er attributes: ? r - read only. ? rwl - read and write when unlocked. values can always be modified via serial eeprom or jtag. values can be written from tlps when the unlock bit is high. ? hwinitwo - hardware initialized write once. th e field may be written once, eeprom or cfg, and then it becomes read only. ho t reset does not reset read only at tribute. cold or warm reset does reset read only attribute. all hwinitwo bits in the same 32 bit register must be written at the same time. ? r/w - read/write. ? r/w1c - read/write 1 to clear; writing a 0 has no effect. these register bits are only set by the peb383. ? rw1cs - sticky read only, write-1-to-clear - not initialized or modified by hot reset. ? r/ws sticky read / write - not initialized or modified by hot reset. ? r/w1s - read 0/write 1 to set (writing a 1 triggers an event such as an in terrupt). these register bits are only cleared by the peb383. ? rc - clear after read. ? rs - sticky read only. not initia lized or modified by hot reset. ? reserved - do not write any value other th an 0 to this field. reads return 0. 14. register descriptions > overview 116 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required ? reservedp - the value in this field mu st be preserved during a write access. ? undefined - this value is undefined after reset because it is based on a bit se tting, a pin setting, or a power-up setting. 14. register descriptions > pci configuration space 117 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.2 pci configuration space the peb383 device uses a standard pci type 1 configuration header. table 32 shows the pci 3.0 compatible type 1 configuration sp ace with constant values shown p opulated in the appropriate header fields. the pcie 1.1 compatible ca pabilities options are located later in the configuration space starting at offset 0xc0 (see table 35 ). the ssid capability registers are shown below. table 32: pci type 1 configuration header 31 0 offset page device id vendor id 0x000 123 status command 0x004 124 class code revision id 0x008 128 bist header type master latency timer cacheline size 0x00c 129 base address register 0(reserved 0x00000000) 0x010 base address register 1 (reserved 0x00000000) 0x014 - secondary latency timer subordinate bus number secondary bus number primary bus number 0x018 130 secondary status i/o limit i/o base 0x01c 131 memory status memory base 0x020 134 prefetchable memory limit prefetchable memory base 0x024 135 prefetchable base upper 32 bits 0x028 136 prefetchable limit upper 32 bits 0x02c 136 i/o limit upper 16 bits i/o base upper 16 bits 0x030 137 reserved capability pointer 0x034 138 expansion rom base address (reserved 0x00000000) 0x038 - bridge control interrupt pin interrupt line 0x03c 139 table 33: ssid capability registers 31 0 offset page reserved next pointer capability id 0x060 160 ssid ssvid 0x064 161 14. register descriptions > pci configuration space 118 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required the power management capability registers are shown below. the pcie capability registers are shown below. the advanced error reporting capa bility register is shown below. table 34: power management capability registers 31 0 offset page power management capabilities next pointer capability id 0x0a0 162 data (reserved 0x00) bridge support extensions (reserved 0x00) pmcsr 0x0a4 164 table 35: pcie capability registers 31 0 offset page pcie capability register next pointer capability id 0x0c0 173 device capability 0x0c4 175 device status device control 0x0c8 177 link capability 0x0cc 180 link status link control 0x0d0 182 table 36: advanced error reporting capability registers 31 0 offset page pcie enhanced capability header 0x100 188 uncorrectable error status register 0x104 189 uncorrectable error mask register 0x108 190 uncorrectable error se verity register 0x10c 191 correctable error status register 0x110 192 correctable error mask register 0x114 193 advanced error capabilities and control register 0x118 194 14. register descriptions > pci configuration space 119 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required header log register 0x11c 195 0x120 195 0x124 196 0x128 196 secondary uncorrectable error status register 0x12c 197 secondary uncorrectable error mask register 0x130 198 secondary uncorrectable error severity register 0x134 199 secondary error capabilities and control register 0x138 200 secondary header log register 0x13c 200 0x140 201 0x144 202 0x148 202 table 36: advanced error reporting capability registers (continued) 31 0 offset page 14. register descriptions > register map 120 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3 register map the following table lists the re gister map for the peb383. table 37: register map offset name see 0x000 pci_id ?pci identification register? 0x004 pci_csr ?pci control and status register? 0x008 pci_class ?pci class register? 0x00c pci_misc0 ?pci miscellaneous 0 register? 0x010 reserved 0x014 reserved 0x018 pci_busnum ?pci bus number register? 0x01c pci_misc1 ?pci secondary status and i/o limit and base register? 0x020 pci_mio_bl ?pci memory base and limit register? 0x024 pci_pfm_bl ?pci pfm base and limit register? 0x028 pci_pfm_b_upper ?pci pfm base upper 32 address register? 0x02c pci_pfm_l_upper ?pci pfm limit upper 32 address register? 0x030 pci_io_upper ?pci i/o address upper 16 register? 0x034 pci_cap ?pci capability pointer register? 0x038 reserved 0x03c pci_misc2 ?pci bridge control and interrupt register? 0x040 sec_retry_cnt ?secondary retry count register? 0x044 pci_misc_csr ?pci miscellaneous control and status register? 0x048 pci_misc_clk_straps ?pci miscellaneous clock straps register? 0x04c upst_pwr_thres ?upstream posted write threshold register? 0x050 cpl_timeout ?completion timeout register? 0x054 clkout_enb_func_dbg ?clock out enable function and debug register? 0x058 serrdis_opqen_dtc ?serrdis_opqen_dtc register? 0x05c reserved 0x060 ssid_cap ?ssid capability register? 0x064 ssid_id ?ssid id register? 14. register descriptions > register map 121 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 0x068 ntma_ctrl ?ntma control register? 0x06c ntma_pri_baseupper ?ntma primary upper base register? 0x070 ntma_sec_lbase ?ntma secondary lower base register? 0x074 ntma_sec_baseupper ?ntma secondary upper base register? 0x078 ntma_sec_limit ?ntma secondary lower limit register? 0x07c ntma_sec_upper_limit ?ntma secondary upper limit register? 0x0a0 pci_pmc ?pci power management capability register? 0x0a4 pci_pmcs ?pci power management control and status register? 0x0a8 reserved 0x0ac ee_ctrl ?eeprom control register? 0x0b0 sbus_devmsk ?secondary bus device mask register? 0x0b4 stc_period ?short-term caching period register? 0x0b8 rtimer_status ?retry timer status register? 0x0bc pref_ctrl ?prefetch control register? 0x0c0 pcie_cap ?pcie capabilities register? 0x0c4 pcie_dev_cap ?pcie device capabilities register? 0x0c8 pcie_dev_csr ?pcie device control and status register? 0x0cc pcie_lnk_cap ?pcie link capabilities register? 0x0d0 pcie_lnk_csr ?pcie link control register? 0x0e4 ar_sbnpctrl ?secondary bus non-prefetchable address remap control register? 0x0e8 ar_sbnpbase ?secondary bus non-prefetchable u pper base address remap register? 0x0ec ar_sbpprectrl ?secondary bus prefetchable address remap control register? 0x0f0 ar_sbprebaseupper ?secondary bus prefetchable upper base address remap register? 0x0f4 ar_pbnpbaseupper ?primary bus non-prefetchable upper base address remap register? 0x0f8 ar_pbnplimitupper ?primary bus non-prefetchable upper limit remap register? 0x0fc reserved 0x100 pcie_aerr_cap ?pcie advanced error reporting capability register? 0x104 pcie_uerr_stat ?pcie uncorrectable error status register? table 37: register map (continued) offset name see 14. register descriptions > register map 122 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 0x108 pcie_uerr_mask ?pcie uncorrectable error mask register? 0x10c pcie_uerr_sev ?pcie uncorrectable error severity register? 0x110 pcie_cor_err ?pcie correctable error status register? 0x114 pcie_cor_mask ?pcie correctable error mask register? 0x118 pcie_aerr_cap_ctrl ?pcie advanced error capabilities and control register? 0x11c pcie_hl1 ?pcie header log 1 register? 0x120 pcie_hl2 ?pcie header log 2 register? 0x124 pcie_hl3 ?pcie header log 3 register? 0x128 pcie_hl4 ?pcie header log 4 register? 0x12c pcie_serr_stat ?pcie secondary uncorrectable error status register? 0x130 pcie_serr_mask ?pcie secondary uncorrectable error mask register? 0x134 pcie_serr_sev ?pcie secondary uncorrectable error severity register? 0x138 pcie_ecap_ctrl ?pcie secondary error capabilities and control register? 0x13c pcie_sec_hl1 ?pcie secondary header log 1 register? 0x140 pcie_sec_hl2 ?pcie secondary header log 2 register? 0x144 pcie_sec_hl3 ?pcie secondary header log 3 register? 0x148 pcie_sec_hl4 ?pcie secondary header log 4 register? 0x14c-204 reserved 0x208 replay_latency ?replay latency register? 0x20c acknak_upd_lat ?ack/nack update latency register? 0x210 n_fts ?n_fts register? table 37: register map (continued) offset name see 14. register descriptions > register map 123 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.1 pci identification register this register contains de vice and vendor identifiers. register name: pci_id reset value: 0x8113_10e3 register offset: 0x000 bits 7 6 5 4 3 2 1 0 31:24 did 23:16 did 15:08 vid 07:00 vid bits name description type reset value 31:16 did device id this field indicates the silicon device identification number. rwl 0x8113 15:0 vid vendor id this field indicates the silicon vendor identification number. by default, the peb383 device reports a value of 0x10e3 indicating the vendor as idt (formerly tundra). rwl 0x10e3 14. register descriptions > register map 124 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.2 pci control and status register this register defines configurable parameters for how devices interact with the pci bus, and indicates status information for pci bus events. register name: pci_csr reset value: 0x_0010_0000 register offset: 0x004 bits 7 6 5 4 3 2 1 0 31:24 d_pe s_serr r_ma r_ta s_ta devsel mdp_d 23:16 tfbbc reserved dev66 cap_l int_stat reserved 15:08 reserved int_dis mfbbc serr_en 07:00 wait peresp vgaps mwi_en sc bm ms ios bits name description type reset value 31 d_pe detected parity error this bit is set by the bridge whenever it receives a poisoned tlp or a tlp with bad ecrc (read completion or write request) on the pcie interface, regardless of the state the parity error response bit in the command register. 0 = data poisoning and bad ecrc not detected by the bridge on its pcie interface 1 = data poisoning or bad ecrc detected by the bridge on its pcie interface r/w1c 0 30 s_serr signaled system error this bit is set when the bridge sends an err_fatal or err_nonfatal message to the root complex and the serr# enable bit is set in the command register. 0 = neither err_fatal nor err_nonfatal transmitted on the pcie interface 1 = err_fatal or err_nonfatal transmitted on the pcie interface r/w1c 0 29 r_ma received master-abort this bit is set when the bridge receives a completion with unsupported request completion status on its pcie interface. 0 = unsupported request completion status not received on the pcie interface 1 = unsupported request completion status received on the pcie interface r/w1c 0 14. register descriptions > register map 125 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 28 r_ta received target-abort this bit is set when the bridge receives a completion with completer abort completion status on its pcie interface. 0 = completer abort completion status not received on the pcie interface 1 = completer abort completion status received on the pcie interface r/w1c 0 27 s_ta signaled target-abort this bit is set when the bridge generates a completion with completer abort completion status in response to a request received on its pcie interface. 0 = completer abort completion not transmitted on the pcie interface 1 = completer abort completion transmitted on the pcie interface r/w1c 0 26:25 devsel devsel# timing this field is not applicable for pcie. it always reads 0. r00 24 mdp_d master data parity error 0 = no uncorrectable data error detected on the pcie interface 1 = uncorrectable data error detected on the pcie interface this field is set by the peb383 if its parity error response enable bit is set and either of the following conditions occurs: ? the peb383 receives a completion marked poisoned on the pcie interface. ? the peb383 poisons a write request on the pcie interface note: if the parity error response enable bit is cleared, this bit is never set. r/w1c 0 23 tfbbc fast back-to-back capable this field is not applicable for pcie. it always reads 0. r0 22 reserved status reserved 1. it always reads 0. r 0 21 dev66 66-mhz capable this field is not applicable for pcie. it always reads 0. r0 20 cap_l capabilities list 1 = capabilities list is supported r1 19 int_stat interrupt status the peb383 does not generate internal interrupts. r0 18:11 reserved reserved r 0x0 (continued) bits name description type reset value 14. register descriptions > register map 126 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10 int_dis interrupt disable the peb383 does not generate internal interrupts. r0 09 mfbbc fast back-to-back enable this field does not apply for pcie bridges. it always reads 0. r0 08 serr_en serr# enable this bit enables reporting of non-fatal and fatal errors to the root complex. in addition, this bit enables transmission by the pcie interface of err_nonfatal and err_fatal error messages on behalf of serr# assertions detected on the pci interface. note that errors are reported if enabled either through this bit or through the pcie specific bits in the device control register. 0 = disable the reporting of bridge non-fatal errors and fatal errors to the root complex. 1 = enable the reporting of bridge non-fatal errors and fatal errors to the root complex. r/w 0 07 wait idsel stepping / wait cycle control this field does not apply for pcie bridges. it always reads 0. r0 06 peresp parity error response enable this bit controls the peb383?s setting of the master data parity error bit in the status register in response to a received poisoned tlp from pcie. 0 = disable the setting of the master data parity error bit. 1 = enable the setting of the master data parity error bit. r/w 0 05 vgaps vga palette snoop this field does not apply for pcie bridges. it always reads 0. r0 04 mwi_en memory write invalidate enable this bit controls the peb383?s ability to translate pcie memory write requests into pci memory write and invalidate transactions. 0 = do not translate memory write requests into pci memory write and invalidate transactions. 1 = promote memory write requests to pci memory write and invalidate transactions. r/w 0 03 sc special cycles this field does not apply for pcie bridges. it always reads 0. r0 02 bm bus master enable this field allows the peb383 to perform bus-mastered transactions on the pcie link. the host or software driver must ensure this bit is set to 1 for correct ntma operation. r/w 0 (continued) bits name description type reset value 14. register descriptions > register map 127 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 01 ms memory space enable this bit controls the peb383?s response as a target to memory accesses on the pcie interface that address a device that resides behind the bridge in both the non-prefetchable and prefetchable memory ranges, or targets a memory-mapped location within the bridge itself. 0 = respond to all memory requests on the pcie interface as unsupported request received. forward all memory requests from the pci interface to the pcie interface. 1 = enable forwarding of memory transactions to the pci interface and any internal function. r/w 0 00 ios i/o space enable this bit controls the peb383?s response as a target to i/o transactions on the pcie interface that address a device that resides behind the bridge. 0 = respond to all i/o requests on the pcie interface with an unsupported request completion. 1 = enable forwarding of i/o requests to the pci interface. r/w 0 (continued) bits name description type reset value 14. register descriptions > register map 128 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.3 pci class register this register indicates the pci classification of the peb383. register name: pci_class reset value: 0x0604_0001 register offset: 0x008 bits 7 6 5 4 3 2 1 0 31:24 base 23:16 sub 15:08 prog 07:00 rid bits name description type reset value 31:24 base base class this field indicates the device is a bridge. r0x06 23:16 sub sub class this field indicates the device is a pci-to-pci bridge. r0x04 15:08 prog program interface this field reads 0 when the legacy bit is clear (see ?pci miscellaneous clock straps register? ), and reads 0x1 when the legacy bit is set. when set to 0x1, it indicates to software that a subtractive decode bridge is present. for more information about legacy mode, see ?legacy mode? . r0x00 07:00 rid revision id this field indicates the hardware silicon revision identifier. rwl 0x01 14. register descriptions > register map 129 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.4 pci miscellaneous 0 register this register controls mi scellaneous pci functions, such as the latency timer value and cacheline size. register name: pci_misc0 reset value: 0x0001_0000 register offset: 0x00c bits 7 6 5 4 3 2 1 0 31:24 bistc sbist reserved ccode 23:16 h_type 15:08 reserved 07:00 cline bits name description type reset value 31 bistc bist capable; 0 = peb383 is not bist capable r0 30 sbist start bist; 0 = peb383 is not bist capable r0 29:28 reserved reserved r 0 27:24 ccode completion code; 0 = peb383 is not bist capable r0 23:16 h_type header type this field indicates the peb383 is a single-function bridge. r0x01 15:08 reserved reserved (latency timer in pci interface) r 0 07:00 cline cacheline size a 04 = 4 x 32-bit word (16 bytes) 08 = 8 x 32-bit word (32 bytes) 10 = 16 x 32-bit word (64 bytes) 20 = 32 x 32-bit word (128 bytes) this field specifies the system cacheline size in units of 32-bit words. it is used by the pci master to determine the pci read transaction - that is, memory read, memory read line, or memory read multiple - it should generate on the pci bus. cline is also used by the pci target to decide how much data to read on the destination bus. note: this field is set to 0 if cline is programmed to a value not specified above. a. software programs the system cacheline size in dword counts. the value programmed is used by the peb383 for prefetching data from memory for memory read line and memory line multiple transactions on the primary bus interface. software should set only one bit at anytime. if multiple bits are set, the register defaults to 0. r/w 0x0 14. register descriptions > register map 130 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.5 pci bus number register register name: pci_busnum reset value: undefined register offset: 0x018 bits 7 6 5 4 3 2 1 0 31:24 s_ltimer s_ltimer_8 23:16 sub_bus_num 15:08 s_bus_num 07:00 p_bus_num bits name description type reset value 31:27 s_ltimer secondary latency timer this value is used by the peb383 to perform burst transfers on the pci interface. the lower 3 bits are hardwired to 0 so that the timer is limited to 8-cycle granularity. this field defines the minimum amount of time in pci clock cycles that the peb383 can retain ownership as a bus master on the pci interface. 00000 = pci reset value r/w undefined 26:24 s_ltimer_8 set to 000 to force 8-cycle increments for the secondary latency timer. r000 23:16 sub_bus_num subordinate bus number the system software programs th is field with the peb383?s highest-numbered downstream secondary bus number. this value is used by the peb383 to respond to type 1 configuration transactions on the primary bus interface. r/w 0x00 15:08 s_bus_num secondary bus number the system software programs this field with the number of the bridge?s immediate downstream secondary bus. this value is used by the peb383 to convert type 1 configuration transactions received on its primary bus interface to type 0 configuration transactions. r/w 0x00 07:00 p_bus_num[7:0] primary bus number the system software writes to this field with the primary bus number of the peb383. r/w 0x00 14. register descriptions > register map 131 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.6 pci secondary status an d i/o limit and base register register name: pci_misc1_p reset value: 0x02a0_0101 register offset: 0x01c bits 7 6 5 4 3 2 1 0 31:24 d_pe s_serr r_ma r_ta s_ta devsel mdp_d 23:16 tfbbc reserved dev66 reserved 15:08 io_la add_cap1 07:00 io_ba add_cap2 bits name description type reset value 31 d_pe data parity error detected this bit reports the detection of an address or data parity error on the peb383?s pci interface. the peb383 sets this bit when it detects one of the following: ? address parity error as a potential target ? data parity error as a target of a write transaction ? data parity error as a master of a read transaction 0 = device did not detect a parity error. 1 = device detected a parity error. r/w1c 0 30 s_serr received system error this bit reports the assertion of pci_serrn on the pci interface. 1 = pci_serrn was detected on the pci interface. 0 = pci_serrn was not detected. r/w1c 0 29 r_ma received master abort this bit reports the detection of a master-abort termination by the peb383 when it is the master of a transaction on its pci interface. 0 = no master-abort detected. 1 = master-abort detected on the pci interface. r/w1c 0 28 r_ta received target abort this bit reports the detection of a target-abort termination by the peb383 when it is the master of a transaction on its pci interface. 0 = no target-abort detected. 1 = target-abort detected on the pci interface. r/w1c 0 14. register descriptions > register map 132 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 27 s_ta signaled target abort the peb383 sets this bit to report the signaling of target-abort as target of a transaction on the pci interface. 0 = no target-abort signaled. 1 = target-abort signaled by the peb383 on its pci interface. r/w1c 0 26:25 devsel device select timing the peb383 uses medium-speed decoding on its pci interface. r01 24 mdp_d master data parity error this bit reports the detection of an uncorrectable data error by the peb383. 0 = no uncorrectable data error detected on the pci interface. 1 = uncorrectable data error detected on the pci interface. r/w1c 0 23 tfbbc fast back-to-back capability 0 = not supported 1 = supported this bit is hardwired to 1 when the secondary bus interface operates in pci mode, indicating that the bridge can decode fast back-to-back transactions when the transactions are from the same master but to different targets. r1 22 reserved reserved r 0 21 dev66 66-mhz capable pci bus this bit is hardwired to 1, indicating that the secondary bus interface can operate at a 66-mhz clock rate. r1 20:16 reserved reserved r 00000 15:12 io_la[3:0] i/o limit address the peb383 uses this field for i/o address decoding. these bits define the upper bound of the address range used by the bridge to forward an i/o transaction from one interface to the other. these 4 bits correspond to address bits <15:12>. the address bits <11:0> are assumed equal to 12?hfff. r/w 0x0 11:08 add_cap1 addressing capability the peb383 supports 32-bit i/o addressing. r0x1 07:04 io_ba[3:0] i/o base address the peb383 uses this field for i/o address decoding. these bits define the lower bound of address range used by the bridge to forward an i/o transaction from one interface to the other. these 4 bits correspond to address bits <15:12>. the address bits <11:0> are assumed equal to 12?h0. r/w 0x0 (continued) bits name description type reset value 14. register descriptions > register map 133 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 03:00 add_cap2 addressing capability the peb383 supports 32-bit i/o addressing. r0x1 (continued) bits name description type reset value 14. register descriptions > register map 134 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.7 pci memory base and limit register register name: pci_mio_bl reset value: 0x0000_0000 register offset: 0x020 bits 7 6 5 4 3 2 1 0 31:24 la 23:16 la reserved 15:08 ba 07:00 ba reserved bits name description type reset value 31:20 la memory limit address this field is used in conjunction with the memory base address for forwarding memory-mapped i/o transactions. these bits define the upper bound for the memory address range. the upper 12 bits correspond to address bits <31:20> of the address range. bits <19:0> of the address range are 0xfffff. r/w 0 19:16 reserved reserved r 0 15:04 ba memory base address this field defines the lower bound of the address range for forwarding memory-mapped i/o transactions. these bits correspond to address bits <31:20> of the address range. the lower 20 address bits (19:0) are 20?h0. r/w 0 03:00 reserved reserved r 0 14. register descriptions > register map 135 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.8 pci pfm base and limit register register name: pci_pfm_bl reset value: 0x0001_0001 register offset: 0x024 bits 7 6 5 4 3 2 1 0 31:24 la 23:16 la add_la_64 15:08 ba 07:00 ba add_ba_64 bits name description type reset value 31:20 la prefetchable memory limit address this field is used in conjunction with memory base address for forwarding memory-mapped i/o transactions. these bits define the upper bound for the memory address range. the upper 12 bits correspond to address bits <31:20> of the address range. bits <19:0> of the address range are 0xfffff. r/w 0 19:16 add_la_64 addressing capability ? memory base address the peb383 supports 64-bit addressing. r0x1 15:04 ba prefetchable memory base address this field defines the lower bound of the prefetchable memory address range. these bits correspond to address bits <31:20> of the prefetchable address range. the lower 20 address bits (19:0) are 20?h0. r/w 0 03:00 add_ba_64 addressing capabili ty ? memory range limit address the peb383 supports 64-bit addressing. r0x1 14. register descriptions > register map 136 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.9 pci pfm base uppe r 32 address register 14.3.10 pci pfm limit upper 32 address register register name: pci_pfm_b_upper reset value: 0x0000_0000 register offset: 0x028 bits 7 6 5 4 3 2 1 0 31:24 ba 23:16 ba 15:08 ba 07:00 ba bits name description type reset value 31:00 ba prefetchable memory base upper 32-bit address this field is used in conjunction with ba in the ?pci pfm base and limit register? to specify the lower bound of the 64-bit prefetchable address range. the 32 bits relate to address bits <63:32> of the prefetchable base address bits. r/w 0x0 register name: pci_pfm_l_upper reset value: 0x0000_0000 register offset: 0x02c bits 7 6 5 4 3 2 1 0 31:24 la 23:16 la 15:08 la 07:00 la bits name description type reset value 31:00 la prefetchable memory limit upper 32-bit address this field is used in conjunction with la in the ?pci pfm base and limit register? to specify the upper bound of the 64-bit prefetchable address range. the 32 bits relate to address bits <63:32> of the prefetchable limit address. r/w 0x0 14. register descriptions > register map 137 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.11 pci i/o address upper 16 register register name: pci_io_upper reset value: 0x0000_0000 register offset: 0x030 bits 7 6 5 4 3 2 1 0 31:24 io_la 23:16 io_la 15:08 io_ba 07:00 io_ba bits name description type reset value 31:16 io_la i/o limit address upper 16-bits this field is used in conjunction with io_la in the ?pci secondary status and i/o limit and base register? to define the upper bound 32-bit address range used for decoding i/o transactions from the pcie interface to the pci interface. these bits relate to address bits <31:16> of i/o limit address. r/w 0x0000 15:00 io_ba i/o base address upper 16-bits this field is used in conjunction with io_ba in the ?pci secondary status and i/o limit and base register? to define the lower bound 32-bit address range used for decoding i/o transaction from the pcie interface to the pci interface. these bits relate to address bits <31:16> of i/o base address. r/w 0x0000 14. register descriptions > register map 138 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.12 pci capability pointer register register name: pci_cap reset value: 0x0000_00a0 register offset: 0x034 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved 07:00 cap_ptr bits name description type reset value 31:08 reserved reserved r 0x0 07:00 cap_ptr capabilities pointer by default the next capability pointer is 0xa0 ?pci power management capability register? . if it is desired to link in ?ssid capability register? then this value should be changed to 0x60. rwl 0x0a0 14. register descriptions > register map 139 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.13 pci bridge contro l and interrupt register register name: pci_misc2 reset value: 0x0000_00ff register offset: 0x03c bits 7 6 5 4 3 2 1 0 31:24 reserved discard _serr discard_ stat discard2 discard1 23:16 s_fptp_ en s_reset ma_err vga_ 16bit_en vga_en isa_en serr_en s_ peresp 15:08 int_pin 07:00 int_line bits name description type reset value 31:28 reserved reserved r 0x0 27 discard_serr discard timer serr# enable this bit only applies in pci mode. it enables the peb383 to generate either an err_nonfatal (by default) or err_fatal transaction on the pcie interface when the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge. the severity is selectable only if advanced error reporting is supported. 0 = do not generate err_nonfatal or err_fatal on the pcie interface as a result of the expiration of the secondary discard timer. note that an error message can still be sent if advanced error reporting is supported and the delayed transaction discard timer expired mask bit is clear. 1 = generate err_nonfatal or err_fatal on the pcie interface if the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge. r/w 0 26 discard_stat discard timer status it is set to 1 when the secondary discard timer expires and a delayed completion is discarded from a queue in the bridge. 0 = no discard timer error 1 = discard timer error r/w1c 0 14. register descriptions > register map 140 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 25 discard2 secondary discard timer this bit determines the number of pci clocks that the bridge waits for a master on the pci interface to repeat a delayed transaction request. the counter starts once the completion (pcie completion associated with the delayed transaction request) has reached the head of the downstream queue of the bridge (that is, all ordering requirements have been satisfied and the bridge is ready to complete the delayed transaction with the originating master on the secondary bus). if the originating master does not repeat the transaction before the counter expires, the bridge deletes the delayed transaction from its queue and sets the discard timer status bit. 0 = secondary discard timer counts 2 15 pci clock cycles 1 = secondary discard timer counts 2 10 pci clock cycles r/w 0 24 discard1 primary discard timer this bit does not apply to pcie. it always reads 0. r0 23 s_fptp_en fast back-to-back enable the peb383 cannot generate fast back-to-back transactions as a master on the pci interface. r0 22 s_reset secondary bus reset this bit forces the assertion of pci_rst# on the pci interface. the secondary pci_rst# is asserted by the bridge whenever this bit is set. the bridge?s secondary bus interface and any buffers between the two interfaces (primary and secondary) must be initialized back to their default state whenever this bit is set. the primary bus interface and all configuration space registers must not be affected by the setting of this bit. because pci_rst# is asserted for as long as this bit is set, software must observe proper pci reset timing requirements. 0 = do not force the assertion of the pci interface pci_rst#. 1 = force the assertion of the pci interface pci_rst#. r/w 0 (continued) bits name description type reset value 14. register descriptions > register map 141 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 21 ma_err master-abort mode this bit controls the behavior of a bridge when it receives a master-abort termination (for example, an unsupported request on pcie) on either interface. 0 = do not report master-aborts. when a ur response is received from pcie for non-posted transactions, and when the secondary side is operating in pci mode, return 0xffff_ffff on reads and complete i/o writes normally. when a master-abort is received on the pci interface for posted transactions initiated from the pcie interface, no action is taken (that is, all data is discarded). 1 = report ur completions from pcie by signaling target-abort on the pci interface when the pci interface is operating in pci mode. for posted transactions initiated from the pcie interface and master-aborted on the pci interface, the bridge must return an err_nonfatal (by default) or err_fatal transaction (provided the serr# enable bit is set in the command register). the severity is selectable only if advanced error reporting is supported. r/w 0 20 vga_16bit_en vga 16-bit enable this bit enables the bridge to provide 16-bit decoding of vga i/o address precluding the decoding of alias addresses every 1 kb. this bit has meaning only if vga enable bit is set. 1 = executes 16-bit address decodes on vga i/o accesses 0 = executes 10-bit address decodes on vga i/o accesses r/w 0 (continued) bits name description type reset value 14. register descriptions > register map 142 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 19 vga_en vga enable this bit modifies the response of the bridge to vga-compatible addresses. if this bit is set, the bridge forwards the following accesses on the pcie interface to the pci interface (and, conversely, block the forwarding of these addresses from the secondary interface to the pcie interface): ? memory accesses in the range 0x000a_0000 to 000b_ffff ? i/o addresses in the first 64 kbytes of the i/o address space (address[31:16] for pcie are 0x0000) and where address[9:0] is in the range of 0x3b0 to 0x3bb or 0x3c0 to 0x3df (inclusive of isa address aliases - address[15:10] may possess any value and is not used in the decoding) if this bit is set, the forwarding of vga addresses is independent of the following: ? the value of the isa enable bit ? the i/o address range and memory address ranges defined by the i/o base and limit registers, the memory base and limit registers, and the prefetchable memory base and limit registers of the bridge the forwarding of vga addresses is qualified by the i/o enable and memory enable bits in the ?pci control and status register? . 0 = do not forward vga compatible memory and i/o addresses from pcie to the pci (addresses defined above) unless they are enabled for forwarding by the defined i/o and memory address ranges. 1 = forward vga compatible memory and i/o addresses (addresses defined above) from pcie to pci (if the i/o enable and memory enable bits are set) independent of the i/o and memory address ranges, and independent of the isa enable bit. r/w 0 (continued) bits name description type reset value 14. register descriptions > register map 143 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 18 isa_en isa enable this bit modifies the response by the peb383 to isa i/o addresses. this applies only to i/o addresses that are enabled by the i/o base and limit registers and are in the first 64 kb of pci i/o address space (0000 0000h to 0000 ffffh). if this bit is set, t he bridge blocks any forwarding from primary to secondary of i/o transactions addressing the last 768 bytes in each 1-kb block. in the opposite direction (secondary to primary), i/o transactions are forwarded if they address the last 768 bytes in each 1-kb block. 0 = forward downstream all i/o addresses in the address range defined by the i/o base and limit registers. 1 = forward upstream isa i/o addresses in the address range defined by the i/o base and limit registers that are in the first 64 kb of pci i/o address space (top 768 bytes of each 1-kb block). r/w 0 17 serr_en serr# enable this bit controls the forwarding of pci serr# assertions to the pcie interface. the peb383 transmits an err_fatal or err_nonfatal cycle on the pcie interface when pci_serrn is asserted on the pci interface. this bit is set when advanced error reporting is supported and the serr# assertion detected mask bit is clear in the ?pcie secondary uncorrectable error mask register? . the serr# enable bit is set in the ?pci control and status register? or the pcie-specific bits are set in the ?pcie device control and status register? of the pcie capability structure. 0 = disable the forwarding of serr# from the pci interface to err_fatal and err_nonfatal (serr# can still be forwarded if the serr advanced error mask bit is cleared). 1 = enable the forwarding of secondary serr# to err_fatal or err_nonfatal. r/w 0 (continued) bits name description type reset value 14. register descriptions > register map 144 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16 s_peresp parity error response enable this bit controls the peb383?s response to uncorrectable address, attribute, and data errors on the pci interface. if this bit is set, the bridge must take its normal action when one of these errors is detected. if this bit is cleared, the bridge must ignore any uncorrectable address, attribute, and data errors that it detects and continue normal operation. note: a bridge must generate parity (or ecc, if applicable) even if parity error reporting is disabled. also, a bridge must always forward data with poisoning from pci to pcie on an uncorrectable pci data error, regardless of the setting of this bit. 0 = ignore uncorrectable address, attribute, and data errors on the pci interface. 1 = enable uncorrectable address, attribute, and data error detection and reporting on the pci interface. r/w 0 15:08 int_pin [7:0] interrupt pin the peb383 does not generate in terrupts. therefore, this register is hardwired to 0x00. r0x00 07:00 int_line [7:0] interrupt line the peb383 does not generate an interrupt. therefore, the register is read only. r0xff (continued) bits name description type reset value 14. register descriptions > register map 145 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.14 secondary retry count register register name: sec_retry_cnt reset value: 0x0000_aa00 register offset: 0x040 bits 7 6 5 4 3 2 1 0 31:24 reserved cgd 23:16 reserved arb reserved park 15:8 dtl3 dtl2 dtl1 dtl0 7:0 reserved sec_rt_cnt bits name description type reset value 31:25 reserved reserved r 0 24 cgd clock gating disable 1: clock gating disabled 0: clock gating enabled when in l1 state internal clocks are gated off by default. r/w 0 23:21 reserved reserved r 0 20 arb external arbiter control 0b0: disable external arbiter 0b1: enable external arbiter hwinitwo 0 19:17 reserved reserved r 0 16 park park bus parking policy 0b0: park on last served device 0b1: park on the bridge hwinitwo 0 15:14 dtl0 delayed transaction limit for pci device 3: 0b01; max one delayed transaction for device 3 0b10; max two delayed transaction for device 3 0b11; max three delayed transaction for device 3 0b00; max four delayed transaction for device 3 r/w 0b10 13:12 dtl0 delayed transaction limit for pci device 2: 0b01; max one delayed transaction for device 2 0b10; max two delayed transaction for device 2 0b11; max three delayed transaction for device 2 0b00; max four delayed transaction for device 2 r/w 0b10 14. register descriptions > register map 146 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11:10 dtl0 delayed transaction limit for pci device 1: 0b01; max one delayed transaction for device 1 0b10; max two delayed transaction for device 1 0b11; max three delayed transaction for device 1 0b00; max four delayed transaction for device 1 r/w 0b10 9:8 dtl0 delayed transaction limit for pci device 0: 0b01; max one delayed transaction for device 0 0b10; max two delayed transaction for device 0 0b11; max three delayed transaction for device 0 0b00; max four delayed transaction for device 0 r/w 0b10 7:4 reserved reserved r 0 3:0 sec_rt_cnt this field defines the number of retries that the peb383 will receive on the secondary bus for a requested transaction, before its internal retry counter expires. when the counter expires, the bridge discards the request. 0000 = counting disabled (no expiration) 0001 = 256 retries before expiration 0010 = 64k retries before expiration 0100 = 16m retries before expiration 1000 = 2g retries before expiration r/w 0000 (continued) bits name description type reset value 14. register descriptions > register map 147 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.15 pci miscellaneous control and status register register name: pci_misc_csr reset value: 0x7d10_1900 register offset: 0x044 bits 7 6 5 4 3 2 1 0 31:24 reserved en_arb en_arb3 en_arb2 en_arb1 en_arb0 reserved p_err 23:16 stc_en reserved arb_pri arb_pri3 arb_pri2 arb_pri1 arb_pri0 15:08 reserved cpl_init_count cfg_rt 07:00 reserved bits name description type reset value 31 reserved reserved r 0 30 en_arb enable internal arbiter this bit enables arbitration for peb383 requests. 0 = peb383 disables internal requests. 1 = peb383 enables internal requests. 0 r/w 1 29 en_arb3 enable arbiter 3 0 = peb383 disables pci_req3n for arbitration. 1 = the bridge enables pci_req3n for arbitration. r/w 1 28 en_arb2 enable arbiter 2 0 = peb383 disables pci_req2# for arbitration. 1 = peb383 enables pci_req2# for arbitration. r/w 1 27 en_arb1 enable arbiter 1 0 = peb383 disables pci_req1# for arbitration. 1 = peb383 enables pci_req1# for arbitration. r/w 1 26 en_arb0 enable arbiter 0 0 = peb383 disables pci_req0# for arbitration. 1 = peb383 enables pci_req0# for arbitration. r/w 1 25 reserved reserved r 0 24 p_err parity error behavior this bit controls the behavior of the peb383 when it detects a data parity error during a non-posted write transaction. 0 = pci_perrn is asserted and the corrupted data is passed. 1 = pci_perrn is asserted and the transaction is asserted on the originating bus, appropriate status bits are set, data is discarded, and the request is not enqueued. r1 14. register descriptions > register map 148 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 23 stc_en short-term caching enable 0 = disable short-term caching 1 = enable short-term caching r/w 0 22:21 reserved reserved r 00 20 arb_pri internal arbiter priority this bit sets priority for peb383 requests. 0 = internal requests from the peb383 are assigned low priority 1 = internal requests from the peb383 are assigned high priority r/w 1 19 arb_pri3 arbiter priority 3 0 = peb383 assigns low priority to pci_req3#. 1 = peb383 assigns high priority to pci_req3#. r/w 0 18 arb_pri2 arbiter priority 2 0 = peb383 assigns low priority to pci_req2#. 1 = peb383 assigns high priority to pci_req2#. r/w 0 17 arb_pri1 arbiter priority 1 0 = peb383 assigns low priority to pci_req1#. 1 = peb383 assigns high priority to pci_req1#. r/w 0 16 arb_pri0 arbiter priority 0 0 = peb383 assigns low priority to pci_req0#. 1 = peb383 assigns high priority to pci_req0#. r/w 0 15 reserved reserved r 0 14:11 cpl_init_count this is applicable for upstream non-posted requests in pci mode. it indicates the number of dwords of response data to be accumulated before starting the data transfer. 0000 = 8 dwords 0001 = 16 dwords 0010 = 24 dwords 0011 = 32 dwords 0100 = 40 dwords 0101 = 48 dwords 0110 = 56 dwords 0111 = 64 dwords 1000 = 72 dwords 1001 = 80 dwords 1010 = 88 dwords r/w 0011 (continued) bits name description type reset value 14. register descriptions > register map 149 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 10:08 cfg_rt configuration retry timer the peb383 returns the completion with crs completion status for the received type 1 configuration requests if this timer is expired before receiving the completion from the targeted secondary device. 000 = 25 us 001 = 40 us 010 = 50 us 011 = 100 us 100 = 200 us 101 = 500 us 110 = 1 ms 111 = 10 ms r/w 001 07:00 reserved reserved r 0x00 (continued) bits name description type reset value 14. register descriptions > register map 150 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.16 pci miscellaneous clock straps register register name: pci_misc_clk_straps reset value: 0x0000_0100 register offset: 0x048 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved csr_sel_ 400 07:00 legacy reserved pcge op_mode cs_mode bits name description type reset value 31:9 reserved reserved r 0 8 csr_sel_400 this bit programs the pll clock: 1 = pll clock is 400mhz. this generates 50/50% nominal pci_clko. 0 = pll clock is 200mhz. this generates 33/66% nominal pci_clko. note: for normal operation, leave this bit in its default state. r/w 1 7 legacy legacy mode when set to 1, the peb383 operates in legacy mode (for more information, see ?legacy mode? ). r/w 0 6:5 reserved reserved r 0 4 pcge pci clock gate enable 0b0: pci_clk[3:0] clock gating disabled 0b1: pci_clk[3:0] clock gating enabled when in d3_hot, and in 33mhz mode. in addition the bits ?bpcce? and ?b2b3s? in the ?pci power management control and status register? is updated to reflect this note : setting this bit to a 1 has no effect if clock rate is higher than 33mhz. r/w 0 3 op_mode operating mode 0 = peb383 provides the clock on pci_clko with the speed defined by the m66_en signal (33/66 mhz) 1 = peb383 provides the clock on pci_clko with the speed defined by the cs_mode bits. (25/33/50/60 mhz) r/w 0 14. register descriptions > register map 151 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 2:0 cs_mode clock speed mode this field defines the clock speed when op_mode is set to 1 according to the following code points: 0bx00 = 25-mhz pci mode 0bx01 = 33-mhz pci mode 0bx10 = 50-mhz pci mode 0bx11 = 66-mhz pci mode r/w 000 (continued) bits name description type reset value 14. register descriptions > register map 152 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.17 upstream posted write threshold register register name: upst_pwr_thres reset value: 0x0000_0307 register offset: 0x04c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved max_buf_aloc 7:0 reserved upst_pwr_thres bits name description type reset value 31:10 reserved reserved. r 0 9:8 max_buf_aloc maximum buffer allocation this field determines the maximum completion buffer allocation that a single, upstream non-posted read request will create.the amount of completion buffer allocated is the min of these bits and the read request. 11 = 1024 bytes 10 = 512 bytes 01 = 256 bytes 00 = 256 bytes r/w 11 7:5 reserved reserved. r 0 4:0 upst_pwr_thres this field defines the threshold for the upstream posted writes, and indicates the length of posted write data to be accumulated in the upstream posted buffer that triggers forwarding of a posted request onto the pcie core. note: other events may also trigger forwarding. for more information, see ?upstream posted buffer? . this field is defined as follows: 00000 = 16 bytes 00001 = 32 bytes 00010 = 48 bytes 00011 = 64 bytes 00100 = 80 bytes 00101 = 96 bytes 00110 = 112 bytes 00111 = 128 bytes r/w 00111 14. register descriptions > register map 153 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.18 completion timeout register register name: cpl_timeout reset value: 0x8009_8968 register offset: 0x050 bits 7 6 5 4 3 2 1 0 31:24 cpl_to_ en cpl_to_value 23:16 cpl_to_value 15:08 cpl_to_value 07:00 cpl_to_value bits name description type reset value 31 cpl_to_en completion timeout enable this bit enables/disables the completion timeout function. the peb383 handles an upstream non-posted request as if completion is returned with ur if the completion is not returned before its completion timeout timer is expired. 0 = disable completion timeout timer 1 = enable completion timeout timer r/w 1 30:00 cpl_to_value completion timeout value this 31-bit register defines the completion timeout value as follows: 0x0000_0000 = 0 ns 0x0000_0001 = 16 ns 0x0000_0002 = 32 ns 0x0000_0003 = 48 ns --------- 0x0009_8968 = 10 ms (default value) 0x7fff_ffff = 34 s r/w 0x009_8968 14. register descriptions > register map 154 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.19 clock out enable function and debug register register name: clkout_enb_func_dbg reset value: 0x0000_1f00 register offset: 0x054 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved clkout_enb 07:00 reserved func_dbg bits name description type reset value 31:13 reserved reserved. r 0 12:08 clkout_enb this field enables and disables the five clocks (pci_clk_out[4:0]) supplied to the pci secondary devices. clkout_enb[0] 0 = disable pci_clk_out[0] 1 = enable pci_clk_out[0] clkout_enb[1] 0 = disable pci_clk_out[1] 1 = enable pci_clk_out[1]clkout_enb[2] 0 = disable pci_clk_out[2] 1 = enable pci_clk_out[2] clkout_enb[3] 0 = disable pci_clk_out[3] 1 = enable pci_clk_out[3] clkout_enb[4] 0 = disable pci_clk_out[4] 1 = enable pci_clk_out[4] r/w 11111 07:02 reserved reserved r 0 01 unlock setting this bit to 0b1 allows register bits with an rwl attribute to be written from tlps, i.e. configuration or memory writes. register bits with rwl attribute can always be written from eeprom or jtag regardless of the setting of this bit. r/w 0 00 func_dbg this bit is for functional testing. setting to 0b1 disables scrambling. r/w 0 14. register descriptions > register map 155 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.3.20 serrdis_opqen_dtc register register name: serrdis_opqen_dtc reset value: 0x0000_0100 register offset: 0x058 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved st_dist_ en reserved sec_dist _en 07:00 reserved bits name description type reset value 31:11 reserved reserved r 0 10 st_dist_en short term discard timer enable 0 = secondary discard timer value sets to either 0x03ff (1k pci clock cycles) or 0x7fff (32 k pci clock cycles) 1 = secondary discard timer value sets to 0x003f (64 pci clock cycles) r/w 0 9 reserved reserved r 0 8 sec_dist_en secondary discard timer enable 0 = disable secondary discard timer 1 = enable secondary discard timer r/w 1 7:0 reserved reserved r 0 14. register descriptions > upstream non- transparent address remapping registers 156 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.4 upstream non-transparent address remapping registers the peb383 supports address remapping, which is one of the requirements of non-transparent bridging. all transactions that fa ll in the non-transparent address ra nge are mapped to different address locations according to follow ing device-specific registers. 14.4.1 ntma control register register name: ntma_ctrl reset value: 0x0000_0000 register offset: 0x068 bits 7 6 5 4 3 2 1 0 31:24 ntma_lba 23:16 ntma_lba reserved 15:08 reserved 07:00 reserved ntma_ rmp reserved bits name description type reset value 31:20 ntma_lba ntma primary lower base address. r/w 0x0 19:04 reserved reserved r 0x0 03 ntma_rmp 0 = disable ntma address remapping. 1 = enable ntma address remapping. r/w 0x0 02:00 reserved reserved r 0x0 14. register descriptions > upstream non- transparent address remapping registers 157 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.4.2 ntma primary upper base register 14.4.3 ntma secondary lower base register register name: ntma_pri_baseupper reset value: 0x0000_0000 register offset: 0x06c bits 7 6 5 4 3 2 1 0 31:24 ntma_uba 23:16 ntma_uba 15:08 ntma_uba 07:00 ntma_uba bits name description type reset value 31:00 ntma_uba ntma primary upper base address. r/w 0x0 register name: ntma_sec_lbase reset value: 0x0000_0000 register offset: 0x070 bits 7 6 5 4 3 2 1 0 31:24 ntma_lba 23:16 ntma_lba reserved 15:08 reserved 07:00 reserved bits name description type reset value 31:20 ntma_lba ntma secondary lower base address. r/w 0x0 19:00 reserved reserved r 0x0 14. register descriptions > upstream non- transparent address remapping registers 158 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.4.4 ntma secondary upper base register 14.4.5 ntma secondary lower limit register register name: ntma_sec_baseupper reset value: 0x0000_0000 register offset: 0x074 bits 7 6 5 4 3 2 1 0 31:24 ntma_uba 23:16 ntma_uba 15:08 ntma_uba 07:00 ntma_uba bits name description type reset value 31:00 ntma_uba ntma secondary upper base address. r/w 0x0 register name: nt ma_sec_lower_limit reset value: 0x0000_0000 register offset: 0x078 bits 7 6 5 4 3 2 1 0 31:24 ntma_lla 23:16 ntma_lla reserved 15:08 reserved 07:00 reserved bits name description type reset value 31:20 ntma_lla ntma secondary lower limit address. r/w 0x0 19:00 reserved reserved r 0x0 14. register descriptions > pci capability registers 159 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.4.6 ntma secondary upper limit register 14.5 pci capability registers the peb383 device supports pci and pcie extended capabilities options. the capabilities pointer field in the ?pci capability pointer register? (0x034) points to the first pci capabilities option, while the first pcie extended capability op tion is always located at 0x100 (see ?pcie advanced error reporting capabi lity register? ). 14.5.1 ssid/ssvid capability the optional ?ssid id register? ? subsystem id (ssid) and subs ystem vendor id (ssvid) id ? uniquely identifies the add-in card or subsystem wher e the pci device resides. it provides a mechanism for add-in card vendors to distingu ish their add-in cards from one anot her even though the add-in cards may have the same pci bridge on them (and, th erefore, the same vendor id and device id). values in this register must be loaded and va lid prior to system soft ware accessing the pci configuration space. note that by default, the ssid capability is not linked in via ?pci capability pointer register? . this capability must be linked in first, befo re the ssid id register can be written. register name: ntma_sec_upper_limit reset value: 0x0000_0000 register offset: 0x07c bits 7 6 5 4 3 2 1 0 31:24 ntma_ula 23:16 ntma_ula 15:08 ntma_ula 07:00 ntma_ula bits name description type reset value 31:00 ntma_ula ntma secondary upper limit address. r/w 0x0 when the peb383 operates in ?legacy mode? the following registers are not supported and are treated as reserved: ? ?pcie capability registers? ? ?advanced error reporting capability registers? 14. register descriptions > pci capability registers 160 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.2 ssid capability register register name: ssid_cap reset value: 0x0000_a00d register offset: 0x060 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 cap_ptr 07:00 cap_id bits name description type reset value 31:16 reserved reserved r 0x0 15:08 cap_ptr capabilities pointer this register contains the head pointer for the capability list in pci configuration space. r0xa0 07:00 cap_id capability id r 0x0d 14. register descriptions > pci capability registers 161 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.3 ssid id register the values in this register can be written by eeprom. register name: ssid_id reset value: 0x0000_0000 register offset: 0x064 bits 7 6 5 4 3 2 1 0 31:24 ssid 23:16 ssid 15:08 ssvid 07:00 ssvid bits name description type reset value 31:16 ssid sub system id this value identifies the add-in card or subsystem, and is assigned by the vendor. rwl 0 15:0 ssvid sub system vendor id this value identifies the manufacturer of the add-in card or subsystem. rwl 0 14. register descriptions > pci capability registers 162 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.4 pci power manageme nt capability register this register defines bytes 0 to 3 of the power management capability option. register name: pci_pmc reset value: 0x7803_c001 register offset: 0x0a0 bits 7 6 5 4 3 2 1 0 31:24 pme_sup d2_sp d1_sp aux_cur 23:16 aux_cur dsi reserved pme_ck pm_ver 15:08 nxt_ptr 07:00 cap_id bits name description type reset value 31:27 pme_sup pme support this field indicates the power management states from which the peb383 device can indicate pme#. the value reported by this field is based on serial eeprom programming that indicates how auxiliary power is routed to the peb383 device in the system. given the right power supplies, the peb383 can assert the pme# signals in d3 cold . in the absence of serial eeprom information, the peb383 will report pme support for power levels down to d3 hot . rwl 01111 26 d2_sp d2 support this field always returns 0 since the peb383 does not support the d2 power management state. r0 25 d1_sp d1 support this field always returns 0 since the peb383 does not support the d1 power management state. r0 24:22 aux_cur aux current this field returns a value 0 indicating the device is self powered. r000 21 dsi device specific initialization hardwired to 0. no special initialization is required. r0 20 reserved reserved. it always reads 0. r 0 19 pme_ck pme clock this field is not applicable to devices with a pcie interface. it always reads 0. r0 14. register descriptions > pci capability registers 163 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 18:16 pm_ver version this field indicates a version number of 011 indicating it supports the pci bus power management interface specification (revision 1.2) . r011 15:8 nxt_ptr next pointer this field points to the next capability option: ?pcie capabilities register? (0x0c0). note: this read-only value will be changed to 0x00 when the legacy bit is set to 1 in the ?pci miscellaneous clock straps register? . r0xc0 7:0 cap_id capability id this field contains the value 0x01 indicating a power management capability option. r0x01 (continued) bits name description type reset value 14. register descriptions > pci capability registers 164 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.5 pci power management control and status register this register defines the control and status regi sters of the power management capability option. register name: pci_pmcs reset value: 0x0000_0008 register offset: 0x0a4 bits 7 6 5 4 3 2 1 0 31:24 data 23:16 bpcce b2b3s reserved 15:08 pme_st data_sc data_sel pme_en 07:00 reserved no_soft_ rst reserved pwr_st bits name description type reset value 31:24 data power data the peb383 does not support the power data field. r0x00 23 bpcce bpcc_en (bus power/clock control enable) - a ?1? indicates that the bus power/clock control mechanism as defined in section 4.7.1 is enabled. a ?0? indicates that the bus power/clock control policies defined in section 4.7.1 have been disabled. when the bus power/clock control mechanism is disabled, the bridge?s pmcsr powerstate field cannot be used by the system software to control the power or clock of the bridge?s secondary bus. this bit will be set if ?pcge? is set in ?pci miscellaneous clock straps register? , and the pci_clk is 33mhz or less. r0x0 22 b2b3s b2_b3# (b2/b3 support for d3hot) - the state of this bit determines the action that is to occur as a direct result of programming the function to d3hot. a ?1? indicates that when the bridge function is programmed to d3hot, its secondary bus?s pci clock will be stopped (b2). a ?0? indicates that when the bridge function is programmed to d3hot, its secondary bus will have its power removed (b3). this bit is only meaningful if bit 7 (bpcc_en) is a ?1?. this bit will be set if ?pcge? is set in ?pci miscellaneous clock straps register? , and the pci_clk is 33mhz or less. r0x0 21:16 reserved reserved. it always reads 0. r 0x0 14. register descriptions > pci capability registers 165 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15 pme_st power pme status this field indicates whether this device can generate pme#. this field?s value is independent of whether the power pme enable field is set to 1. 0 = no pme# is being asserted by this pci function. 1 = a pme# status is reported by this pci function. if pme_en is also set to 1, this pci function is also asserting the pme# signal. writing 1 to this field clears the field. note: the peb383 does not support this feature; this bit always returns a 0. r0 14:13 data_sc power data scale this field always returns 0 since the peb383 device does not support the data field. r00 12:9 data_sel power data select this field always returns 0 since the peb383 device does not support the data field. r0x0 8 pme_en power pme enable this field enables pme# assertion. the initial value of this field depends on whether the device woke from power-off or d3 cold . ? from power-off, this field starts disabled. ?from d3 cold , this field contains the enable condition going into the d3 cold state. 0 = disable pme# generation. 1 = enable pme# generation. r/w 0 7:4 reserved reserved 1. it always reads 0. r 0x0 3 no_soft_rst power no soft reset this field indicates whether the device needs a soft reset after transitioning from d3 hot to d0. this field always returns 1 indicating a soft reset is not required. r1 2 reserved power reserved 0. it always reads 0. r 0 1:0 pwr_st power state this field determines the current power state of the pci function, and sets a new state. if the new state is not supported, the change is ignored. 00 = d0 01 = d1 10 = d2 11 = d3 hot r/w 0 (continued) bits name description type reset value 14. register descriptions > pci capability registers 166 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.6 eeprom control register register name: ee_ctrl reset value: undefined register offset: 0x0ac bits 7 6 5 4 3 2 1 0 31:24 reserved cmd add_width busy cmd_vld 23:16 add 15:08 add 07:00 data bits name description type reset value 31:30 reserved reserved r 0x0 29:28 cmd command 01 = read 10 = write r/w 0x0 27:26 add_width address width this field indicates the address width of the serial eeprom, and whether or not an eeprom device is present. 00 = no eeprom 01 = 9-bit address 10 = 16-bit address note: a blank eeprom is indicated with 0b00. if this occurs, these bits must be written with the appropriate values before the eeprom can be accessed. r/w undefined 25 busy this bit indicates the serial eeprom is busy with read/write operation. software must poll this bit before initiating a write/read to the external eeprom through a configuration write to the ?eeprom control register? . for informatio n on software polling, see ?system diagram? . r0x0 24 cmd_vld this bit validates the command and side-band signals to the serial eeprom. r/w 0x0 23:08 add address this is the eeprom address to be read from or written into. r/w 0x0000 07:00 data data this is the data to be written into the eeprom. r/w 0x00 14. register descriptions > pci capability registers 167 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.7 secondary bus device mask register this register provides a method to support private devices on the pci bus. the process of converting type 1 configuration transactions to type 0 configur ation transactions is modified by the contents of this register. a confi guration transaction that targets a device ma sked by this regist er is rerouted to device 15. setting this register to all zeros disables device masking. register name: sbus_devmsk reset value: 0x0000_0000 register offset: 0x0b0 bits 7 6 5 4 3 2 1 0 31:24 reserved devmsk_ 13 reserved devmsk_9 reserved 23:16 devmsk_7 devmsk_6 devmsk_5 devmsk_4 reserved devmsk_1 reserved 15:08 reserved 07:00 reserved bits name description type reset value 31:30 reserved reserved r 0 29 devmsk_13 device mask 13 0 = rerouting disabled for device 13. 1 = block assertion of pci_ad (pin 29) for configuration transactions to device 13, assert pin pci_ad (pin 31) instead. r/w 0 28:26 reserved reserved. masking for devices 12, 11, and 10 is not implemented. operation of the peb383 is unaffected by the value of these bits. r0 25 devmsk_9 device mask 9 0 = rerouting disabled for device 9. 1 = block assertion of pci_ad (pin 25) for configuration transactions to device 9, assert pin pci_ad (pin 31) instead. r/w 0 24 reserved reserved. masking for device 8 is not implemented. operation of the peb383 is unaffected by the value of this bit. r0 23 devmsk_7 device mask 7 0 = rerouting disabled for device 7. 1 = block assertion of pci_ad (pin 23) for configuration transactions to device 7, assert pin pci_ad (pin 31) instead. r/w 0 14. register descriptions > pci capability registers 168 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 22 devmsk_6 device mask 6 0 = rerouting disabled for device 6. 1 = block assertion of pci_ad (pin 22) for configuration transactions to device 6, assert pin pci_ad (pin 31) instead. r/w 0 21 devmsk_5 device mask 5 0 = rerouting disabled for device 5. 1 = block assertion of pci_ad (pin 21) for configuration transactions to device 5, assert pin pci_ad (pin 31) instead. r/w 0 20 devmsk_4 device mask 4 0 = rerouting disabled for device 4. 1 = block assertion of pci_ad (pin 20) for configuration transactions to device 4, assert pin pci_ad (pin 31) instead. r/w 0 19:18 reserved reserved. masking for devices 3 and 2 is not implemented. operation of the peb383 is unaffected by the value of these bits. r0 17 devmsk_1 device mask 1 0 = rerouting disabled for device 1. 1 = block assertion of pci_ad (pin 17) for configuration transactions to device 1, assert pin pci_ad (pin 31) instead. r/w 0 16:0 reserved reserved. operation of the peb383 is unaffected by the value of these bits. r0 (continued) bits name description type reset value 14. register descriptions > pci capability registers 169 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.8 short-term caching period register register name: sterm_caching_period reset value: 0x0000_0040 register offset: 0x0b4 bits 7 6 5 4 3 2 1 0 31:24 st_cache 23:16 st_cache 15:08 st_cache 07:00 st_cache bits name description type reset value 31:00 st_cache short term caching period this field indicates the number of pci clock cycles allowed before short-term caching is discarded. r/w 0x0000_ 0040 14. register descriptions > pci capability registers 170 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.9 retry timer status register register name: timer_status reset value: 0x0000_0000 register offset: 0x0b8 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved 07:00 reserved sec_dis_ stat reserved sec_r_ stat bits name description type reset value 31:03 reserved reserved r 0x0 2 sec_dis_stat secondary discard timer status for more information on this timer, see discard2 in ?pci bridge control and interrupt register? . 0 = secondary discard timer has not expired. 1 = secondary discard timer has expired. r0 1 reserved reserved r 0 0 sec_r_stat secondary retry timer status for more information on this timer, see ?secondary retry count register? . 0 = secondary retry timer has not expired 1 = secondary retry timer has expired r0 14. register descriptions > pci capability registers 171 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.5.10 prefetch control register register name: pref_ctrl reset value: 0x0300_0041 register offset: 0x0bc bits 7 6 5 4 3 2 1 0 31:24 reserved p_mr p_mrl p_mrm 23:16 mrl_66 mrl_33 15:08 mrl_33 mrm_66 07:00 mrm_66 mrm_33 bits name description type reset value 31:27 reserved reserved r 0x00 26 p_mr 0 = the peb383 fetches a dword of data in case of 32-bit pci data bus mode. 1 = the peb383 prefetches as per the value specified in mrl_66/mrl_33 fields on behalf of the pci master for memory read command. r/w 0 25 p_mrl 0 = the peb383 prefetches one cacheline of data. 1 = the peb383 prefetches as per the value specified in mrl_66/mrl_33 fields on behalf of the pci master for memory read line command. r/w 1 24 p_mrm 0 = the peb383 prefetches two cachelines of data. 1 = the peb383 prefetches as per the value specified in mrm_66/mrm_33 fields on behalf of pci master for memory read multiple command. r/w 1 23:18 mrl_66 this bit indicates the threshold parameter for memory read line and memory read commands in 66-mhz pci mode. unit is 64-byte chunk. 6?h00 = 64 bytes 6?h01 = 128 bytes ... 6?h3f = 4096 bytes r/w 0x00 17:12 mrl_33 this bit indicates the threshold parameter for memory read line and memory read commands in 33-mhz pci mode. unit is 64-byte chunk. 6?h00 = 64 bytes 6?h01 = 128 bytes ... 6?h3f = 4096 bytes r/w 0x00 14. register descriptions > pci capability registers 172 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 11:6 mrm_66 this bit indicates the threshold parameter for memory read multiple command in 66-mhz pci mode. unit is 64-byte chunk. 6?h00 = 64 bytes 6?h01 = 128 bytes ... 6?h3f = 4096 bytes r/w 0x01 5:0 mrm_33 this bit indicates the threshold parameter for memory read multiple command in 33-mhz pci mode. unit is 64-byte chunk. 6?h00 = 64 bytes 6?h01 = 128 bytes ... 6?h3f = 4096 bytes r/w 0x01 (continued) bits name description type reset value 14. register descriptions > pcie capability registers 173 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.6 pcie capability registers in the peb383, the pcie capability is located in pci 2.3 configuration space at 0x0c0 and contains 20 bytes. 14.6.1 pcie capabilities register the pcie capabilities register defines bytes 0 to 3 of the pcie capability option. when the peb383 operates in ?legacy mode? the following registers are not supported and are treated as reserved: ? ?pcie capability registers? ? ?advanced error reporting capability registers? register name: pcie_cap reset value: 0x0071_0010 register offset: 0x0c0 bits 7 6 5 4 3 2 1 0 31:24 reserved int_mn slot_imp 23:16 dp_type cap_ver 15:08 nxt_ptr 07:00 cap_id bits name description type reset value 31:30 reserved pcie reserved. it always reads 0. r 00 29:25 int_mn pcie interrupt message number the peb383 device does not have slot status or root port status. it always reads 0. r 00000 24 slot_imp pcie slot implemented this field is not applicable for a bridge device. it always reads 0. r0 23:20 dp_type pcie device port type this field indicates the device is a pcie bridge device. r 0111 19:16 cap_ver pcie capability version this field returns a version number of 1 indicating it supports pcie 1.1 capabilities. r 0001 15:08 nxt_ptr next pointer this field points to the next capability option. in the peb383, this will contain a value of 0x00 indicating there are no more pci compatible capabilities options. r0x00 14. register descriptions > pcie capability registers 174 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 07:00 cap_id capability id this field contains the value 0x10 indicating a pcie capability option. r0x10 (continued) bits name description type reset value 14. register descriptions > pcie capability registers 175 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.6.2 pcie device ca pabilities register this register defines bytes 4 to 7 of the pcie capability option. register name: pcie_dev_cap reset value: 0x0000_8000 register offset: 0x0c4 bits 7 6 5 4 3 2 1 0 31:24 reserved pl_scl pl_val 23:16 pl_val reserved 15:08 rol_bas_ err_rep reserved l1_lat l0s_lat 07:00 l0s_lat ext_tag ph_func max_size bits name description type reset value 31:28 reserved pcie reserved. it always reads 0. r 0000 27:26 pl_scl pcie captured slot power limit scale this field specifies the scale used for the slot power limit value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x this value is set by the set_slot_power_limit message. the default value is 00. r00 25:18 pl_val pcie captured slot power limit value in combination with the slot power limit scale value, this field specifies the upper limit on power supplied by the slot. power limit (in watts) calculated by multiplying the value in this field by the value in the slot power limit scale field. this value is set by the set_slot_power_limit message. the default value is 0x00. r0x00 17:16 reserved pcie reserved. it always reads 0. r 000 15 rol_bas_err_ rep role-based error reporting this bit, when set, indicates that the device uses the functionality defined in the error reporting ecn for the pcie base specification, (revision 1.0a ), and later incorporated into the pci express base specification (revision 1.1) . this bit must be set by all devices conforming to the ecn, pcie 1.1 specification, or subsequent pcie base specification revisions. r1 14. register descriptions > pcie capability registers 176 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14:12 reserved the value read from these bits is 0b000. previous version of the pci specification had defined theses bits, they are now defined as read only, and return 0b000. system software is permitted to write any value to these bits. r000 11:9 l1_lat pcie endpoint l1 acceptable latency this field indicates the acceptable latency for transition from l1 to l0 state. this field is set to 0b000 since the peb383 is not an endpoint. r000 8:6 l0s_lat pcie endpoint l0s acceptable latency this field indicates the acceptable latency for transition from l0s to l0 state. this field is set to 0b000 since the peb383 is not an endpoint. r000 5 ext_tag pcie extended tag field supported this field contains the value 0 indicating 5-bit tag fields are supported. r0 4:3 ph_func pcie phantom functions supported this field is 0 indicating no phantom functions are used. r00 2:0 max_size pcie maximum payload size supported 000 = 128 bytes r000 (continued) bits name description type reset value 14. register descriptions > pcie capability registers 177 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.6.3 pcie device contro l and status register this register defines bytes 8 to 11 of the pcie capability option. register name: pcie_dev_csr reset value: 0x0000_2000 register offset: 0x0c8 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved tran_ pnd aux_pwr _dtd uns_req_ dtd ftl_err_ dtd nftl_ err_dtd cor_err _dtd 15:08 cfg_retr y_en max_rd_size en_snp_ nreq aux_pwr _pm_en phn_en ext_tag_ en 07:00 max_pay_size en_rlx_ ord uns_req_ en ftl_err_ en nftl_ err_en cor_err _en bits name description type reset value 31:22 reserved pcie reserved. it always reads 0. r 0x000 21 tran_pnd pcie transaction pending this field indicates the peb383 issued non-posted requests that have not been completed. 0 = no pending completion of non-posted requests. 1 = pending completion of non-posted requests. r0 20 aux_pwr_dtd pcie aux power detected this field indicates whether the peb383 detected aux power. the peb383, however, do es not require the auxiliary power. 0 = no aux power detected. 1 = aux power detected. r0 19 uns_req_dtd pcie unsupported request detected this field indicates whether an unsupported request was detected. 0 = no error detected. 1 = error detected. writing 1 clears this error. r/w1c 0 18 ftl_err_dtd pcie fatal error detected this field indicates whether a fatal error was detected. 0 = no error detected. 1 = error detected. writing 1 clears this error. r/w1c 0 14. register descriptions > pcie capability registers 178 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 17 nftl_err_dtd pcie n on-fatal error detected this field indicates whether a non-fatal error was detected. 0 = no error detected. 1 = error detected. writing 1 clears this error. r/w1c 0 16 cor_err_dtd pcie correctable error detected this field indicates whether a correctable error was detected. 0 = no error detected. 1 = error detected. writing 1 clears this error. r/w1c 0 15 cfg_retry_en bridge configuration retry enable 0 = disable the peb383 to return configuration request retry status (crs) in response to configuration requests to the target devices below the bridge. 1 = enable the peb383 to return configuration request retry status (crs) in response to configuration requests to the target devices below the bridge. r/w 0 14:12 max_rd_size pcie max read request size this field sets the maximum read request size for the peb383 as a requestor. 000 = 128 bytes 001 = 256 bytes 010 = 512 bytes 011 = 1024 bytes 100 = 2048 bytes 101 = 4096 bytes 110-111 = reserved. r/w 010 11 en_snp_nreq pcie enable snoop not required the peb383 does not set the no snoop attribute. this bit is hardwired to 0. r0 10 aux_pwr_pm_ en pcie aux power pm enable when this bit is set the pe b383 can draw aux power independent of pme aux power. 0 = do not allow use of aux power other than pme aux. 1 = allow use of aux power other than pme aux. r/w 0 9 phn_en pcie phantom functions enable the peb383 does not use phantom functions. this bit always returns 0. r0 8 ext_tag_en pcie extended tag field enable the peb383 does not support extended tag fields. this bit always returns 0. r0 (continued) bits name description type reset value 14. register descriptions > pcie capability registers 179 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 7:5 max_pay_size pcie maximum payload size this field indicates the maximum payload size that can be used for data transmission by the peb383. this must be a subset of the size reported by max_size in ?pcie device capabilities register? . 000-111 = 128 bytes r/w 000 4 en_rlx_ord pcie enable relaxed ordering this field controls whether relaxed ordering for transactions is enabled. 0 = relaxed ordering is disabled. 1 = relaxed ordering is enabled. r0 3 uns_req_en pcie unsupported request reporting enable this field controls reporting of unsupported requests. 0 = no error reporting. 1 = error reporting enabled. r/w 0 2 ftl_err_en pcie fatal error reporting enable this bit, in conjunction with other bits, controls sending err_fatal messages (for more information, see figure 22 ). 0 = no error reporting. 1 = error reporting enabled. r/w 0 1 nftl_err_en pcie non-fatal error reporting enable this bit, in conjunction with other bits, controls sending err_nonfatal messages (for more information, see figure 22 ). 0 = no error reporting. 1 = error reporting enabled. r/w 0 0 cor_err_en pcie correctable error reporting enable this bit, in conjunction with other bits, controls sending err_cor messages (for more information, see figure 22 ). 0 = no error reporting. 1 = error reporting enabled. r/w 0 (continued) bits name description type reset value 14. register descriptions > pcie capability registers 180 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.6.4 pcie link capabilities register register name: pcie_lnk_cap reset value: 0x0001_3c11 register offset: 0x0cc bits 7 6 5 4 3 2 1 0 31:24 port_num 23:16 reserved dll_lnk_ act_rep_ cap srp_dwn _err_rep _cap clk_pwr_ mgt l1_exit 15:08 l1_exit l0s_exit aspm max_width 07:00 max_width max_speed bits name description type reset value 31:24 port_num pcie port number the peb383 always reports a port number of 0 for this field. r0x00 23:21 reserved pcie reserved. this field always reads 0. r 0x00 20 dll_lnk_act_ rep_cap data link layer link active reporting capable for a downstream port, this bit must be set to 1 if the component can report the dl_active state of the data link control and management state machine. for a hot-plug capable downstream port, this bit must be set to 1. for upstream ports and components that do not support this capability, this bit must be hardwired to 0. note: the peb383 does not support dll_lnk_act_rep_cap. this field always reads 0. r0 19 srp_dwn_err_ rep_cap surprise down erro r reporting capable for a downstream port, this bit must be set to 1 if the component can detect and report a surprise down error condition. for upstream ports and components that do not support this capability, this bit must be hardwired to 0. note: the peb383 does not support srp_dwn_err_rep_cap. this field always reads 0. r0 14. register descriptions > pcie capability registers 181 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 18 clk_pwr_mgt clock power management 0 = the component does not have this capability, and the reference clock(s) must not be removed in these link states. 1 = the component tolerates the removal of any reference clock(s) via the ?clock request? (clkreq#) mechanism when the link is in the l1 and l2/3 ready link states. this capability is applicable only in form factors that support ?clock request? (clkreq#) capability. for a multifunction device, each function indicates its capability independently. power management configuration software must only permit reference clock removal if all functions of the multifunction device indicates a 1 in this bit. note: the peb383 does not support clk_pwr_mgt. this field always reads 0. r0 17:15 l1_exit pcie l1 exit latency l1 exit latency is between 2 and 4 us. rwl 010 14:12 l0s_exit pcie l0s exit latency the peb383 l0s exit latency will be as 256-512ns which will be reported as 0b011. this value can be overwritten by the serial eeprom. 000 = less than 64 ns 001 = 64 ns to less than 128 ns 010 = 128 ns to less than 256 ns 011 = 256 ns to less than 512 ns 100 = 512 ns to less than 1 us 101= 1 us to less than 2us 110 = 2-4 us 111 = more than 4 us rwl 011 11:10 aspm pcie aspm support the peb383 supports the l0s and l1 aspm state. this field always returns 11. r11 09:04 max_width pcie maximum link width this field indicates the maximum number of pcie lanes that can be used for communicating with the peb383. 0x01 = 1 pcie lane r0x01 03:00 max_speed pcie maximum link speed this field is always 1 indicating a 2.5-gbps link. r0x1 (continued) bits name description type reset value 14. register descriptions > pcie capability registers 182 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.6.5 pcie link control register this register defines bytes 16 to 17 of the pcie capability option. register name: pcie_lnk_csr reset value: 0x0011_0000 register offset: 0x0d0 bits 7 6 5 4 3 2 1 0 31:24 reserved dll_lnk_ act slt_clk_ config reserved neg_lnk_width 23:16 neg_lnk_width lnk_speed 15:08 reserved 07:00 e_sync com_clk retrain l nk_dis rcb reserved aspm_ctl bits name description type reset value 31:30 reserved reserved r 00 29 dll_lnk_act data link layer active. this bit indicates the status of the data link control and management state machine. this bit is hardwired to 0. r0 28 slt_clk_config slot clock configuration. this bit indicates the peb383 uses the same physical reference clock that the platform provides on the connector. this bit can be loaded from the serial eeprom as part of the pcb configuration information. r0 27:26 reserved reserved r 0 25:20 neg_lnk_width negotiated link width. this field indicates the negotiated width of the pcie link. 000001 = x1 lane r0x01 19:16 lnk_speed link speed. this field indicates the negotiated link speed of the pcie link. 0001 = 2.5-gbps pcie link r0x1 15:8 reserved reserved r 0x00 7 e_sync pcie extended synchronization this field is normally only used when attempting to capture the pcie link on an analyzer since it allows the synchronization cycle to be extended allowing the analyzer to synchronize to the link. 0 = normal operation. 1 = enable extended synchronization r/w 0 14. register descriptions > pcie capability registers 183 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6 com_clk pcie common clock configuration this field selects between a distributed common reference clock or an asynchronous reference clock. after setting both ends of the link to the same value, the link must be retrained from the bridge side of the link. components use this common clock configuration information to report the correct l0s and l1 exit latencies. 0 = asynchronous reference clock 1 = distributed common reference clock r/w 0 5 retrain pcie retrain link this field is reserved for a bridge device. it always reads 0. r0 4 lnk_dis pcie link disable this field is reserved for a bridge device. it always reads 0. r0 3 rcb pcie read completion boundary this field is set by system software to indicate the read completion boundary value of the upstream root port. 0 = 64 bytes 1 = 128 bytes r/w 0 2 reserved pcie reserved. it always reads 0. r 0 1:0 aspm_ctl pcie aspm control this field enables different levels of aspm. 00: disabled 01 :l0s entry enabled 10: l1 entry enabled 11: l0s and l1 entry enabled r/w 00 (continued) bits name description type reset value 14. register descriptions > downstream no n-transparent address remapping registers 184 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.7 downstream non-transp arent address remapping registers 14.7.1 secondary bus non-prefetchab le address remap control register register name: ar_sbnpctrl reset value: 0x0000_0000 register offset: 0x0e4 bits 7 6 5 4 3 2 1 0 31:24 sec_np_lbase 23:16 sec_np_lbase reserved 15:08 reserved io_size 07:00 reserved np_rema pp_en reserved bits name description type reset value 31:20 sec_np_lbase secondary non-pref etchable lower base. r/w 0x000 19:13 reserved reserved. r 0x00 12:8 io_size this field describes how many upper bits of a downstream i/o address are discarded. r/w 0x00 7:4 reserved reserved. r 0x0 3 np_remapp_en 1 = enable non-prefetchable address remapping r/w 0x0 2:0 reserved reserved. r 0x0 14. register descriptions > downstream no n-transparent address remapping registers 185 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.7.2 secondary bus non-prefetchable upper base address remap register 14.7.3 secondary bus prefetchable address remap control register register name: ar_sbnpbase reset value: 0x0000_0000 register offset: 0x0e8 bits 7 6 5 4 3 2 1 0 31:24 sec_np_uba 23:16 sec_np_uba 15:08 sec_np_uba 07:00 sec_np_uba bits name description type reset value 31:00 sec_np_uba secondary bus non-p refetchable upper base. r/w 0x000 register name: ar_sbpprectrl reset value: 0x0000_0000 register offset: 0x0ec bits 7 6 5 4 3 2 1 0 31:24 sec_pre_lba 23:16 sec_pre_lba reserved 15:08 reserved 07:00 reserved pre_rem ap_en reserved bits name description type reset value 31:20 sec_pre_lba secondary bus pr efetchable lowerbase. r/w 0x000 19:4 reserved reserved. r 0x0000 3 pre_remap_en 0 = disable prefetchable address remapping 1 = enable prefetchable address remapping r/w 0x0 2:0 reserved reserved. r 0x0 14. register descriptions > downstream no n-transparent address remapping registers 186 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.7.4 secondary bus prefetchable upper base address remap register 14.7.5 primary bus non-prefetchable upper base address remap register register name: ar_sbprebaseupper reset value: 0x0000_0000 register offset: 0x0f0 bits 7 6 5 4 3 2 1 0 31:24 sec_pre_uba 23:16 sec_pre_uba 15:08 sec_pre_uba 07:00 sec_pre_uba bits name description type reset value 31:00 sec_pre_uba secondary bus non-p refetchable upper base. r/w 0x000 register name: ar_pbnpbaseupper reset value: 0x0000_0000 register offset: 0x0f4 bits 7 6 5 4 3 2 1 0 31:24 pri_np_uba 23:16 pri_np_uba 15:08 pri_np_uba 07:00 pri_np_uba bits name description type reset value 31:00 pri_np_uba primary bus non-prefetchable upper base. r/w 0x0000_000 0 14. register descriptions > downstream no n-transparent address remapping registers 187 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.7.6 primary bus non-prefetchab le upper limit remap register register name: ar_pbnplimitupper reset value: 0x0000_0000 register offset: 0x0f8 bits 7 6 5 4 3 2 1 0 31:24 pri_np_ula 23:16 pri_np_ula 15:08 pri_np_ula 07:00 pri_np_ula bits name description type reset value 31:00 pri_np_ula primary bus non-prefetchable upper limit r/w 0x0000_000 0 14. register descriptions > advanced error reporting capability registers 188 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8 advanced error reporting capability registers 14.8.1 pcie advanced error re porting capabili ty register when the peb383 operates in ?legacy mode? the following registers are not supported and are treated as reserved: ? ?pcie capability registers? ? ?advanced error reporting capability registers? register name: pcie_adv_err_cap reset value: 0x0001_0001 register offset: 0x100 bits 7 6 5 4 3 2 1 0 31:24 nxt_cap_off 23:16 nxt_cap_off cap_ver 15:08 ext_cap_id 07:00 ext_cap_id bits name description type reset value 31:20 nxt_cap_off next capability offset this field contains the offset to the next pcie capability structure or 0x000 if no other items exist in the linked list of capabilities. for extended capabilities implemented in device configuration space, this offset is relative to the beginning of pci compatible configuration space and thus must always be either 0x000 (for terminating list of capabilities) or greater than 0x0ff. r0x000 19:16 cap_ver capability version this field is a pci-sig defined version number that indicates the version of the capability structure present. r0x1 15:0 ext_cap_id pcie extended capability id this field is a pci-sig defined id number that indicates the function and format of the extended capability. the extended capability id for the advanced error reporting capability is 0x0001. r 0x0001 14. register descriptions > advanced error reporting capability registers 189 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.2 pcie uncorrectable error status register register name: pcie_unc_err_stat reset value: 0x0000_0000 register offset: 0x104 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved ur ecrc mal_tlp rxo uxc 15:08 ca cto fcpe ptlp reserved 07:00 reserved dlpe reserved undefined bits name description type reset value 31:21 reserved reserved r 0x000 20 ur unsupported request error status r/w1cs 0 19 ecrc ecrc error status r/w1cs 0 18 mal_tlp malformed tlp status r/w1cs 0 17 rxo receiver overflow status r/w1cs 0 16 uxc unexpected completion status r/w1cs 0 15 ca completer abort status r/w1cs 0 14 cto completion timeout status r/w1cs 0 13 fcpe flow control protocol error status r/w1cs 0 12 ptlp poisoned tlp status r/w1cs 0 11:5 reserved reserved r 0x00 4 dlpe data link protocol error status r/w1cs 0 3:1 reserved reserved r 000 0 undefined undefined r 0 14. register descriptions > advanced error reporting capability registers 190 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.3 pcie uncorrectabl e error mask register register name: pcie_uerr_mask reset value: 0x0000_0000 register offset: 0x108 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved ur ecrc mal_tlp rxo uxc 15:08 ca cto fcpe ptlp reserved 07:00 reserved dlpe reserved undefined bits name description type reset value 31:21 reserved reserved r 0x000 20 ur unsupported request error mask r/ws 0 19 ecrc ecrc error mask r/ws 0 18 mal_tlp malformed tlp mask r/ws 0 17 rxo receiver overflow mask r/ws 0 16 uxc unexpected completion mask r/ws 0 15 ca completer abort mask r/ws 0 14 cto completion timeout mask r/ws 0 13 fcpe flow control protocol error mask r/ws 0 12 ptlp poisoned tlp mask r/ws 0 11:5 reserved reserved r 0x00 4 dlpe data link protocol error mask r/ws 0 3:1 reserved reserved r 000 0 undefined undefined r 0 14. register descriptions > advanced error reporting capability registers 191 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.4 pcie uncorrectable error severity register register name: pcie_unc_err_sev reset value: 0x0006_2030 register offset: 0x10c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved ur ecrc mal_tlp rxo uxc 15:08 ca cto fcpe ptlp reserved 07:00 reserved sdes dlpe reserved unused bits name description type reset value 31:21 reserved reserved r 0x000 20 ur unsupported request error severity r/ws 0 19 ecrc ecrc error severity r/ws 0 18 mal_tlp malformed tlp severity r/ws 1 17 rxo receiver overflow severity r/ws 1 16 uxc unexpected completion severity note : in the pci express base specification (revision 1.1) , unexpected completions are only reported as correctable errors: this bit should not be set to 1. r/ws 0 15 ca completer abort severity r/ws 0 14 cto completion timeout severity r/ws 0 13 fcpe flow control protocol error severity r/ws 1 12 ptlp poisoned tlp severity r/ws 0 11:6 reserved reserved r 0x00 5 sdes surprise down error severity r/ws 1 4 dlpe data link protocol error severity r/ws 1 3:1 reserved reserved r 000 0 unused reserved note : bit 0 is training error status for pcie 1.0a, but is not defined for the pci express base specification (revision 1.1) . r0 14. register descriptions > advanced error reporting capability registers 192 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.5 pcie correctable error status register register name: pcie_cor_err reset value: 0x0000_0000 register offset: 0x110 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved anfe rt_to reserved rn_ro 07:00 b_dllp b_tlp reserved rxe bits name description type reset value 31:14 reserved reserved r 0x00000 13 anfe advisory non-fatal error status r/w1cs 0 12 rt_to replay timer timeout status r/w1cs 0 11:9 reserved reserved r 000 8 rn_ro replay_num rollover status r/w1cs 0 7 b_dllp bad dllp status this bit is set to indicate the following conditions: ? calculated crc was not equal to received crc. r/w1cs 0 6 b_tlp bad tlp status this bit is set to indicate the following conditions: ? physical layer indicated errors with the tlp ? tlp ended with edb, but calculated crc was not the logical not of the received crc ? calculated crc was not equal to the received crc r/w1cs 0 5:1 reserved reserved r 0x0 0 rxe receiver error status r/w1cs 0 14. register descriptions > advanced error reporting capability registers 193 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.6 pcie correctable error mask register register name: pcie_cor_mask reset value: 0x0000_2000 register offset: 0x114 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved anfe rt_to reserved rn_ro 07:00 b_dllp b_tlp reserved rxe bits name description type reset value 31:14 reserved reserved r 0x00000 13 anfe advisory non-fatal error mask r/ws 1 12 rt_to replay timer timeout mask r/ws 0 11:9 reserved reserved r 000 8 rn_ro replay_num rollover mask r/ws 0 7 b_dllp bad dllp mask r/ws 0 6 b_tlp bad tlp mask r/ws 0 5:1 reserved reserved r 0x0 0 rxe receiver error mask r/ws 0 14. register descriptions > advanced error reporting capability registers 194 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.7 pcie advanced error capabi lities and control register register name: pcie_adv_err_cap_ctrl reset value: 0x0000_00a0 register offset: 0x118 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved ec_en 07:00 ec_cap eg_en eg_cap err_ptr bits name description type reset value 31:9 reserved reserved r 0x0000_00 8 ec_en ecrc check enable 0 = disable 1 = enable r/ws 0 7 ec_cap ecrc check capable this bit indicates the peb383 can check ecrc. r1 6 eg_en ecrc generation enable 0 = disable 1 = enable r/ws 0 5 eg_cap ecrc generation capable this bit indicates the peb383 can generate ecrc. r1 4:0 err_ptr first error pointer this pointer is a read-only field that identifies the bit position of the first error reported in the ?pcie uncorrectable error status register? . rs 0 14. register descriptions > advanced error reporting capability registers 195 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.8 pcie header log 1 register 14.8.9 pcie header log 2 register register name: pcie_hl1 reset value: 0x0000_0000 register offset: 0x11c bits 7 6 5 4 3 2 1 0 31:24 header[127:120] 23:16 header[119:112] 15:08 header[111:104] 07:00 header[103:96] bits name description type reset value 31:00 header[127:96] header of tlp associated with error. rs 0 register name: pcie_hl2 reset value: 0x0000_0000 register offset: 0x120 bits 7 6 5 4 3 2 1 0 31:24 header[95:88] 23:16 header[87:80] 15:08 header[79:72] 07:00 header[71:64] bits name description type reset value 31:00 header[95:64] header of tlp associated with error. rs 0 14. register descriptions > advanced error reporting capability registers 196 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.10 pcie header log 3 register 14.8.11 pcie header log 4 register register name: pcie_hl3 reset value: 0x0000_0000 register offset: 0x124 bits 7 6 5 4 3 2 1 0 31:24 header[63:56] 23:16 header[55:48] 15:08 header[47:40] 07:00 header[39:32] bits name description type reset value 31:00 header[63:32] header of tlp associated with error. rs 0 register name: pcie_hl4 reset value: 0x0000_0000 register offset: 0x128 bits 7 6 5 4 3 2 1 0 31:24 header[31:24] 23:16 header[23:16] 15:08 header[15:08] 07:00 header[07:00] bits name description type reset value 31:00 header[31:00] header of tlp associated with error. rs 0 14. register descriptions > advanced error reporting capability registers 197 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.12 pcie secondary uncorrect able error status register register name: pcie_sec_uerr_stat reset value: 0x0000_0000 register offset: 0x12c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved ib_err se rr_ad perr_ad dtdte uadd_ err uatt_err 07:00 uderr uscm usce reserved r_ma r_ta ma_sc ta_sc bits name description type reset value 31:14 reserved reserved r 0x0000_0 13 ib_err internal bridge error status (no header log). the peb383 never sets this bit. r0 12 serr_ad serr# assertion detected (no header log) r/w1cs 0 11 perr_ad perr# assertion detected r/w1cs 0 10 dtdte delayed transaction discard timer expired status (no header log) r/w1cs 0 9 uadd_err uncorrectable address error status r/w1cs 0 8 uatt_err uncorrectable attribute error status r/w1cs 0 7 uderr uncorrectable data error status r/w1cs 0 6 uscm uncorrectable split completion message data error status a a. the peb383 never sets this bit since it does not support pci-x. r/w1cs 0 5 usce unexpected split completion error status a r/w1cs 0 4 reserved reserved r 0 3 r_ma received master-abort status r/w1cs 0 2 r_ta received target-abort status r/w1cs 0 1 ma_sc master-abort on split completion status a r/w1cs 0 0 ta_sc target-abort on split completion status a r/w1cs 0 14. register descriptions > advanced error reporting capability registers 198 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.13 pcie secondary uncorr ectable error mask register register name: pcie_sec_uerr_mask reset value: 0x0000_17a8 register offset: 0x130 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved ib_err se rr_ad perr_ad dtdte uadd_ err uatt_err 07:00 uderr uscm usce reserved r_ma r_ta ma_sc ta_sc bits name description type reset value 31:14 reserved reserved r 0x0000_0 13 ib_err internal bridge error mask (no header log) r/ws 0 12 serr_ad serr# assertion detected mask (no header log) r/ws 1 11 perr_ad perr# asserti on detected mask r/ws 0 10 dtdte delayed transaction discard timer expired mask (no header log) r/ws 1 9 uadd_err uncorrectable address error mask r/ws 1 8 uatt_err uncorrectable attribute error mask r/ws 1 7 uderr uncorrectable data error mask r/ws 1 6 uscm uncorrectable split completion message data error mask a a. this bit has no effect on the peb383 since it does not support pci-x. r/ws 0 5 usce unexpected split completion error mask a r/ws 1 4 reserved reserved r 0 3 r_ma received master-abort mask r/ws 1 2 r_ta received target-abort mask r/ws 0 1 ma_sc master-abort on split completion mask a r/ws 0 0 ta_sc target-abort on split completion mask a r/ws 0 14. register descriptions > advanced error reporting capability registers 199 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.14 pcie secondary uncorrect able error severity register register name: pcie_sec_uerr_sev reset value: 0x0000_1340 register offset: 0x134 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved ib_err se rr_ad perr_ad dtdte uadd_ err uatt_err 07:00 uderr uscm usce reserved r_ma r_ta ma_sc ta_sc bits name description type reset value 31:14 reserved reserved r 0x0000_0 13 ib_err internal bridge error severity (no header log) r/ws 0 12 serr_ad serr# assertion detected severity (no header log) r/ws 1 11 perr_ad perr# assertion detected severity r/ws 0 10 dtdte delayed transaction discard timer expired severity (no header log) r/ws 0 9 uadd_err uncorrectable address error severity r/ws 1 8 uatt_err uncorrectable attribute error severity r/ws 1 7 uderr uncorrectable data error severity r/ws 0 6 uscm uncorrectable split completion message data error severity a a. this bit has no effect on the peb383 since it does not support pci-x. r/ws 1 5 usce unexpected split completion error severity a r/ws 0 4 reserved reserved r 0 3 r_ma received master-abort severity r/ws 0 2 r_ta received target-abort severity r/ws 0 1 ma_sc master-abort on split completion severity r/ws 0 0 ta_sc target-abort on split completion severity r/ws 0 14. register descriptions > advanced error reporting capability registers 200 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.15 pcie secondary error capa bilities and control register 14.8.16 pcie secondary header log 1 register register name: pcie_err_cap_ctrl reset value: 0x0000_0000 register offset: 0x138 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved 07:00 reserved sufep bits name description type reset value 31:05 reserved reserved r 0 04:00 sufep secondary uncorrectable first error pointer. rs 0x00 register name: pcie_sec_hl1 reset value: 0x0000_0000 register offset: 0x13c bits 7 6 5 4 3 2 1 0 31:24 tran_att[31:24] 23:16 tran_att[23:16] 15:08 tran_att[15:08] 07:00 tran_att[07:00] bits name description type reset value 31:00 tran_att[31:00] transaction attribute this field is [31:0] of the 36-bit value transferred on c/be[3:0]# and ad[31:0] during the attribute phase. rs 0x0 14. register descriptions > advanced error reporting capability registers 201 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.17 pcie secondary header log 2 register register name: pcie_sec_hl2 reset value: 0x0000_0000 register offset: 0x140 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved tran_cu 07:00 tran_cl tran_att[35:32] bits name description type reset value 31:12 reserved reserved r 0 11:08 tran_cu transaction command upper this value is transferred on c/be[3:0]# during the second address phase of a dac transaction. rs 0x0 07:04 tran_cl transaction command lower this value is transferred on c/be[3:0]# during the first address phase. rs 0x0 3:0 tran_att[35:32] transaction attribute this field is [35:32] of the 36-bit value transferred on c/be[3:0]# and ad[31:0] during the attribute phase. rs 0x0 14. register descriptions > advanced error reporting capability registers 202 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.18 pcie secondary header log 3 register 14.8.19 pcie secondary header log 4 register register name: pcie_sec_hl3 reset value: 0x0000_0000 register offset: 0x144 bits 7 6 5 4 3 2 1 0 31:24 tran_add[31:24] 23:16 tran_add[23:16] 15:08 tran_add[15:08] 07:00 tran_add[07:00] bits name description type reset value 31:00 tran_add[31:00] transaction address this is the first 32 bits of the 64-bit value transferred on ad[31:0] during the first and second address phases. the first address phase is logged in this field, and the second address is logged in ?pcie secondary header log 4 register? . rs 0x0 register name: pcie_sec_hl4 reset value: 0x0000_0000 register offset: 0x148 bits 7 6 5 4 3 2 1 0 31:24 tran_add[63:56] 23:16 tran_add[55:48] 15:08 tran_add[47:40] 07:00 tran_add[39:32] bits name description type reset value 31:00 tran_add[63:32] transaction address this is the second 32 bits of the 64-bit value transferred on ad[31:0] during the first and second address phases. the first address phase is logged in ?pcie secondary header log 3 register? , and the second address phase is logged in this field. in the case of a 32-bit address, this field is set to 0. rs 0x0 14. register descriptions > advanced error reporting capability registers 203 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.20 replay latency register register name: replay_latency reset value: 0x0000_0000 register offset: 0x208 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 replay_l at_en replay_latency 07:00 replay_latency bits name description type reset value 31:16 reserved reserved r 0 15 replay_lat_en replay latency enable r/w 0 14:00 replay_latency replay latency timer value is overwritten by this value if replay_lat_en is set to b1. r/w 0x0000 14. register descriptions > advanced error reporting capability registers 204 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.21 ack/nack update latency register register name: acknak_upd_lat reset value: 0x0009_0009 register offset: 0x20c bits 7 6 5 4 3 2 1 0 31:24 update_ lat_en reserved update_latency 23:16 update_latency 15:08 acknak_ lat_en reserved acknak_latency 07:00 acknak_latency bits name description type reset value 31 update_lat_en update latency enable r/w 0x0 30:28 reserved reserved. r 0 27:16 update_latency update latency timer value is overwritten with this value if update_lat_en is set to b1. r/w 0x009 15 acknak_lat_en ack/nak latency enable r/w 0x0 14:13 reserved reserved. r 0 12:00 acknak_latency ack/nak latency timer value is overwritten with this value if acknak_lat_en is set to b1. r/w 0x0009 14. register descriptions > advanced error reporting capability registers 205 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.8.22 n_fts register register name: n_fts reset value: 0x0000_0020 register offset: 0x210 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:08 reserved 07:00 n_fts bits name description type reset value 31:08 reserved reserved r 0x0 07:00 n_fts this register indicates the n_fts count value to be advertised to the other end component. note: this value should fall in the l0s exit latency value range reported by the peb383. r/w 0x20 14. register descriptions > advanced error reporting capability registers 206 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 207 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9 pcie and serdes control and status registers the following table outlines the pcie serdes and pc s layer registers. these registers are mainly for status reporting and testing. caution should be taken when modifying any of these registers during normal operation. any unused offset sp ace should be treated as reserved. 14.9.1 base offset address calculation the pcie serdes control register addressees are calculated accord ing to the following formula. address = base + offset base = 0x800 the serdes control and status registers must no t be accessed if the serdes is in reset nor when the reference clock is stopped. table 38: serdes per-lane and clock control and status register map offset register name see ?pcie per-lane transmit and receive registers? 0x000 pcie_txrx_stat_0 ?pcie transmit and receive status register? 0x004 pcie_out_stat_0 ?pcie output status and transmit override register? 0x008 pcie_rx_ovrd_0 ?pcie receive and output override register? 0x00c pcie_dbg_ctl ?pcie debug and pattern generator control register? 0x02c pcie_pm_ctl ?pcie pattern matcher control and error register? 0x030 pcie_ss_ec_ctl ?pcie ss phase and error counter control register? 0x034 pcie_sctl_fi ?pcie scope control and frequency integrator register? ?pcie clock module control and status registers? 0x420 pcie_ctl_stat ?pcie control and level status register? 0x428 pcie_ctl_ovrd ?pcie control and level override register? > pcie and serdes control and status registers 208 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.2 pcie per-lane tran smit and receive registers 14.9.3 pcie transmit and receive status register this register reflects the default state of the serdes transmit and receive contro l inputs at power-up. its reset value depends on various inputs. when its accompanying override registers are used, however (see ?pcie output status and tr ansmit overri de register? and ?pcie receive and output override register? ), the relevant status bi ts are no longer valid. register name: pcie_txrx_stat reset value: undefined register offset: 0x000 bits 7 6 5 4 3 2 1 0 31 : 24 reserved los_ctl reserved 23 : 16 rx_eq_val reserved rx_align _en reserved half_ rate 15:08 reserved tx_boost 07:00 tx_boost reserved bits name description type reset value 31:30 reserved reserved r 01 29:28 los_ctl los filtering mode control r undefined 27:24 reserved reserved r undefined 23:21 rx_eq_val receive equalization control r 0b010 20 reserved reserved r 0 18:17 reserved reserved r undefined 16 half_rate digital half-rate data control r undefined 15:10 reserved reserved r 100000 9:6 tx_boost transmit boost control programmed boost value (ratio of drive level of transition bit to non-transition bit) is: boost = -20*log(1-(tx_boost[3:0]+0.5)/32)db, except that setting tx_boost to 0 produces 0db of boost. this produces results up to 5.75db in steps of ~0.37db. r 0b1011 5:0 reserved reserved r undefined > pcie and serdes control and status registers 209 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.4 pcie output status and transmit override register this register indicates th e status of output signals. its rese t value depends on various inputs. the register also provides a method for overriding the value of tx_boost in the ?pcie transmit and receive status register? . register name: pcie_out_stat reset value: undefined register offset: 0x004 bits 7 6 5 4 3 2 1 0 31 : 24 ovrd reserved tx_boost 23 : 16 tx_boost reservedp 15:08 reservedp 07:00 reservedp los reserved bits name description type reset value 31 ovrd enable override of relevant bits 16:30 in this register. r/w 0 30:26 reserved reserved r/w 00000 25:22 tx_boost transmit boost control programmed boost value (ratio of drive level of transition bit to non-transition bit) is: boost = -20*log(1-(tx_boost[3:0]+0.5)/32)db, except that setting tx_boost to 0 produces 0db of boost. this produces results up to 5.75db in steps of ~0.37db. r/w 0x0 21:3 reservedp preserve state on writes. r/w undefined 2 los loss of signal output r undefined 1:0 reserved reserved r undefined > pcie and serdes control and status registers 210 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.5 pcie receive and ou tput override register this register provides a meth od for overriding the values of los_ctl, rx_eq_val, and rx_align_en in the ?pcie transmit and receive status register? . register name: pcie_rx_ovrd reset value: undefined register offset: 0x008 bits 7 6 5 4 3 2 1 0 31 : 24 reservedp 23 : 16 reservedp 15:08 reservedp ovrd_2 los_ctl reservedp 07:00 rx_eq_val reservedp rx_align _en reservedp half_ rate bits name description type reset value 31:15 reservedp preserve state on writes. r undefined 14 ovrd_2 enable override of relevant bits 0:13 in this register. r/w 0 13:12 los_ctl los filtering mode control 00 = disabled 01-10 = reserved 11 = heavy filtering. the los signal is synchronous to the output of the prescaler. heavy filtering means 128 +/- 5 cycles of no signal for los to be asserted. r/w 01 11:8 reservedp preserve state on writes. r/w undefined 7:5 rx_eq_val receive equalization control internal linear equalizer boost is approximately = (rx_eq_val+1)*0.5db example: 3?b100 = 2.5db boost r/w 000 4 reservedp preserve state on writes. r/w 1 3 rx_align_en enable word alignment 0 = alignment (framer) disabled 1 = alignment enabled r/w 1 2:1 reservedp preserve state on writes. r/w 11 0 half_rate digital half-rate data control r/w 0 > pcie and serdes control and status registers 211 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.6 pcie debug and pattern generator control register this register controls the pa ttern generator in the serdes. register name: pcie_dbg_ctl reset value: 0x0000_0000 register offset: 0x00c bits 7 6 5 4 3 2 1 0 31 : 24 reserved pato 23 : 16 pato trigger_ err mode 15:08 reserved 07:00 reserved bits name description type reset value 31:30 reserved reserved r 0 29:20 pato pattern for modes 3?5 program the desired pattern in these 10 bits when using modes 3-5. note: this field returns to its reset value on reset. r/w 0x00 19 trigger_err insert a single error into a lsb note: this field returns to its reset value on reset. r/w 0 18:16 mode pattern to generate: 0 = disabled 1 = lfsr15 (x 15 +x 14 +1) 2 = lfsr7 (x 7 +x 6 +1) 3 = fixed word (pat0) 4 = dc balanced word (pat0, ~pat0) 5 = fixed pattern: (000, pat0, 3ff, ~pat0) 6?7 = reserved r/w 000 15:0 reserved reserved r 0 > pcie and serdes control and status registers 212 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.7 pcie pattern matcher control and error register this register controls the pattern matcher in the serdes. register name: pcie_pm_ctl reset value: undefined register offset: 0x02c bits 7 6 5 4 3 2 1 0 31 : 24 ov14 count 23 : 16 count 15:08 reserved 07:00 reserved sync mode bits name description type reset value 31 ov14 overflow 14 0 = inactive 1 = multiply count by 128 if ov14 is 1 and count=2^15-1, signals overflow of counter. note: this bit may require two reads to get a stable value. a a. read operation on this register is pipelined. two reads may be needed to get ?current? value. the value is volatile; that is, the value may change at any time.the second read resets the counter. r/w undefined 30:16 count current error count if ov14 field is active, then multiply count by 128. a r/w undefined 15:4 reserved reserved r 0 3 sync synchronize pattern matcher lfsr with incoming data must be turned on then off to enable checking. note: this bit returns to its reset value on reset r/w 0 2:0 mode pattern to match: 0 = disabled 1 = lfsr15 2 = lfsr7 3 = d[n] = d[n-10] 4 = d[n] = !d[n-10] 5-7 = reserved r/w 000 > pcie and serdes control and status registers 213 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.8 pcie ss phase and erro r counter control register this register holds the current mpll phase selector value and information for the associated error counter in the serdes. register name: pcie_ss_ec_ctl reset value: undefined register offset: 0x030 bits 7 6 5 4 3 2 1 0 31 : 24 reserved ss_pval 23 : 16 ss_pval dthr 15:08 ov14 count 07:00 count bits name description type reset value 31:28 reserved reserved r 0 27:17 ss_pval phase value from zero reference a a. read operation on this register is pipelined. two reads may be needed to get ?current? value. the value is volatile; that is, the value may change at any time.the second read resets the counter. r/w 0x000 16 dthr bits below the useful resolution a r/w 0 15 ov14 0verflow 14 0 = inactive 1 = multiply count by 128. if ov14=1 and count=2^15-1, signals overflow of counter. a r/w undefined 14:0 count current error count if ov14 field is active, then multiply count by 128. a r/w undefined > pcie and serdes control and status registers 214 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.9 pcie scope control and fr equency integrator register register name: pcie_sctl_fi reset value: 0000_0000 register offset: 0x034 bits 7 6 5 4 3 2 1 0 31 : 24 reserved 23 : 16 reserved 15:08 reserved fval 07:00 fval dthr_f bits name description type reset value 31:14 reserved reserved r/w 0 13:1 fval frequency is 1.526*val ppm from the reference. value is a signed integer format (2?s complement). note: this field may require two ?reads? to get a stable value. r/w 0 0 dthr_f bits below the useful resolution. note: this bit may require two ?reads? to get a stable value. r/w 0 > pcie and serdes control and status registers 215 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.10 pcie clock module co ntrol and status registers 14.9.11 pcie control and level status register this register indicates th e status of various control inputs. its reset value depends on inputs. when its accompanying override register is used, however (see ?pcie control and leve l override register? ), the relevant status bits are no longer valid. register name: pcie_ctl_stat reset value: undefined register offset: 0x420 bits 7 6 5 4 3 2 1 0 31 : 24 reserved tx_lvl los_lvl 23 : 16 los_lvl acjt_lvl 15:08 reserved 07:00 reserved bits name description type reset value 31 reserved reserved r 1 30:26 tx_lvl fine resolution setting of tx signal level. equation: pk-pk output level (without attenuation) = 1230 x (48 + tx_lvl/2)/63.5 mv vdiff-pp note: tx_lvl should be set to >= 0x1010 (which results in an output of 1vp-p). for more information on available settings, see table 39 . r0x10 25:21 los_lvl loss of signal detector level. r 0x12 20:16 acjt_lvl ac jtag comparator level. r 0x00 15:0 reserved reserved r 1 > pcie and serdes control and status registers 216 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 14.9.12 pcie control and level override register the register provides a method for overriding the value of tx_lvl, los_lvl, and acjt_lvl in the ?pcie control and leve l status register? . register name: pcie_ctl_ovrd reset value: undefined register offset: 0x428 bits 7 6 5 4 3 2 1 0 31 : 24 ovrd tx_lvl los_lvl 23 : 16 los_lvl acjt_lvl 15:08 reserved 07:00 reserved bits name description type reset value 31 ovrd override all level controls. r/w 0 30:26 tx_lvl fine resolution setting of tx signal level. equation: pk-pk output level (without attenuation) = 1230 x (48 + tx_lvl/2)/63.5 mv vdiff-pp note: tx_lvl should be set to >= 0x1010 (which results in an output of 1vp-p). for more information on available settings, see table 39 . r/w 0x10 25:21 los_lvl loss of signal detector level r/w 0x10 20:16 acjt_lvl ac jtag receiver comparator level this sets the hysteresis level for ac jtag. for information on setting the correct voltage levels, see ieee 1149.6. r/w 0x10 15:0 reservedp preserve state on writes. r/w undefined table 39: tx_lvl values tx_lvl value tx_lvl[0:4] vdiff-pp (mv) 0 0x00 5'b00000 929.8 1 0x01 5'b00001 939.4 2 0x02 5'b00010 949.1 3 0x03 5'b00011 958.8 4 0x04 5'b00100 968.5 5 0x05 5'b00101 978.2 > pcie and serdes control and status registers 217 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 6 0x06 5'b00110 987.9 7 0x07 5'b00111 997.6 8 0x08 5'b01000 1007.2 9 0x09 5'b01001 1016.9 10 0xa 5'b01010 1026.6 11 0xb 5'b01011 1036.3 12 0xc 5'b01100 1046.0 13 0xd 5'b01101 1055.7 14 0xe 5'b01110 1065.4 15 0xf 5'b01111 1075.0 16 0x10 5'b10000 1084.7 17 0x11 5'b10001 1094.4 18 0x12 5'b10010 1104.1 19 0x13 5'b10011 1113.8 20 0x14 5'b10100 1123.5 21 0x15 5'b10101 1133.1 22 0x16 5'b10110 1142.8 23 0x17 5'b10111 1152.5 24 0x18 5'b11000 1162.2 25 0x19 5'b11001 1171.9 26 0x1a 5'b11010 1181.6 27 0x1b 5'b11011 1191.3 28 0x1c 5'b11100 1200.9 29 0x1d 5'b11101 1210.6 30 0x1e 5'b11110 1220.3 31 0x1f 5'b11111 1230.0 table 39: tx_lvl values (continued) tx_lvl value tx_lvl[0:4] vdiff-pp (mv) > pcie and serdes control and status registers 218 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 219 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15. electrical characteristics topics discussed include the following: ? ?absolute maximum ratings? ? ?recommended operating conditions? ? ?power characteristics? ? ?power supply sequencing? ? ?dc operating characteristics? ? ?ac timing specifications? ? ?ac timing waveforms? 15.1 absolute maximum ratings table 40: absolute maximum ratings ? pci symbol parameter minimum maximum units t stg storage temperature -55 125 o c t c case temperature under bias -40 120 o c voltage with respect with ground v dd 1.05v dc core logic supply voltage -0.5 2.0 v v dd_pcie 1.05v dc pcie digital supply voltage -0.3 1.7 v v dda_pll 1.05v dc pll analog supply voltage -0.5 2.0 v v dd_pci 3.3v dc i/o supply voltage -0.5 4.1 v v dda_pcie 3.3v dc pcie analog supply voltage -0.5 4.6 v v io_pci pci interface i/o voltage -0.5 6.6 v v il minimum signal input voltage -0.5 - v v ih maximum signal input voltage - v dd a + 0.5 a. the v dd reference is dependent on the input pad supply rail. v 15. electrical characteristics > recommended operating conditions 220 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.2 recommended operating conditions 15.3 power characteristics table 42: recommended operating conditions symbol parameter minimum maximum units notes v dd_pci 3.3v dc i/o supply voltage 3.0 3.6 v - v dda_pcie 3.3v dc pcie supply voltage 3.0 3.6 v - v dd 1.05v dc core supply voltage 0.945 1.155 v - v dd_pcie 1.05v dc pcie digital supply voltage 0.945 1.155 v - v dda_pll 1.05v dc pll supply voltage 0.945 1.155 v - v io_pci pci interface i/o voltage v dd_pci 5.25 v - v ripple1 power supply ripple for voltage supplies: v dd and v dd_pci - 100 mv pp - v ripple2 power supply ripple for voltage supplies: v dd_pcie , v dda_pcie , v dda_pll -50mv pp - t a ambient temperature 0 85 o c a , b a. no heat sink, no air flow. b. higher ambient temperatures are permissible provided t junc is not violated. for heat sink and air flow requirements for higher temperature operation, see ?thermal characteristics? . t junc junction temperature -40 125 o c- table 43: peb383 power dissipation device state aspm link state bridge activity typical power (w) max power (w) d0 l0 fully active links 0.398 0.458 d0 l0 50% link activity 0.312 0.359 d0 l0 0% link activity 0.225 0.259 d0 l0s pcie link in active standby 0.185 0.213 d3hot l1 power saving mode 0.132 0.151 15. electrical characteristics > power supply sequencing 221 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.4 power supply sequencing the peb383 does not have any po wer sequencing constraints. 15.5 dc operating characteristics d3hot l1 power saving mode. all pci clocks gated 0.128 0.148 d3cold n/a power removed 0.060 0.069 table 44: peb383 power dissipation per supply device state aspm link state bridge activity typical power (w) 1.0v_a (w) 3.3v_a (w) 1.0v (w) 3.3v (w) d0 l0 fully active links 0.398 0.022 0.065 0.036 0.275 d0 l0 0% link activity 0.225 0.022 0.065 0.031 0.108 table 45: dc operating characteristics symbol parameter condition minimum maximum units notes v ol_pci pci output low voltage i ol = 1500ua - 0.1v dd_pci v- v oh_pci pci output high voltage i oh = -500ua 0.9v dd_pci -v- v oh_33 3.3 cmos output high voltage i oh = -6ma v dd_pci - 0.5 - v - v ol_33 3.3 cmos output low voltage i ol = 6ma - 0.4 v - v ih_33 3.3 cmos input high voltage -2v dd_pci + 0.5 v - table 43: peb383 power dissipation (continued) device state aspm link state bridge activity typical power (w) max power (w) 15. electrical characteristics > ac timing specifications 222 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.6 ac timing specifications this section discusses ac timing specifications for the peb383. 15.6.1 pci interface ac signal timing v il_33 3.3 cmos input low voltage --0.50.8v- c in_pci input pin capacitance --8.8pf - c clk_pci clock pin capacitance pci_clk --7.5pf- l in_pci input pin inductance --8.3nh - l clk_pci clock pin inductance pci_clk - -4.9nh- table 46: pci clock (p ci_clk) specification symbol parameter min max units notes t f_pci pci clock frequency 25 66 mhz a a. the clock frequency may not change beyond the spread-spectrum limits except while device reset is asserted. t c_pci pci clock cycle time 15 40 ns a b b. the minimum clock period must not be violated for any single clock cycle. t ch_pci pci clock high time 6 - ns - t cl_pci pci clock low time 6 - ns - t sr_pci pci clock slew rate 1 6 v/ns c c. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. t skew pci output clock skew - 0.5 ns - spread spectrum requirements f mod_pci pci_clk clock modulation frequency 30 33 khz - f spread_pci pci_clk clock frequency spread -1 0 % - table 45: dc operating characteristics (continued) symbol parameter condition minimum maximum units notes 15. electrical characteristic s > ac timing specifications 223 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.6.2 pcie differential tran smitter output specification the following table lists the specification of parameters for the differential output of the pcie lanes. table 47: pcie differential transmitter output specification symbol parameter min. nom. max. units comments ui unit interval 399.88 400 400.12 ps each ui is 400ps +/-300ppm. ui does not account for ssc dictated variations. see note 1. v tx-diffp-p differential peak to peak output voltage programmed to tx_lvl=5b?01001 and tx_boost = 0 0.800 - 1.2 v v tx-diffp-p = 2*|v tx-d+ - v tx-d- | see note 1. v tx-de-ratio de-emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db this is the ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note 2 t tx-eye minimum tx eye width 0.75 - - ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 - t tx-eye = 0.25 ui. this parameter is measured with the equivalent of a zero jitter reference clock. see notes 2 and 3. t tx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.125 ui jitter is defined as the measurement variation of the crossing points (v tx-diff = 0v) in relation to recovered tx ui. to be measured after the clock recovery function in section 4.3.3.2 of the pci express base specification rev 1.1 . see notes 2 and 3. t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 - - ui see notes 2 and 5. v tx-cm-acp rms ac peak common mode output voltage -- 20mv v tx-cm-acp = rms(|v tx-d+ + v tx-d- |/2 - v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 see note 2 v tx-cm-dc-active- idle-delta absolute delta of dc common mode voltage during l0 and electrical idle 0- 100mv |v tx-cm-dc [during l0] -v tx-cm-dc [during electrical idle] | <= 100mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [l0] v tx-cm-idle-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [electrical idle] see note 2 15. electrical characteristics > ac timing specifications 224 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required v tx_cm-line -delta absolute delta of dc common mode voltage between d+ and d- 0- 25mv |v tx-cm-dc-d+ -v tx-cm-dc-d+ | <= 25mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | see note 2 v tx-idle-diffp electrical idle differential peak output voltage 0- 20mv v tx-idle-diffp = |v tx-idle-d+ - v tx-idle-d- | <= 20mv see note 2. v tx-rcv-detect the amount of voltage change allowed during receiver detection -- 600mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see section 4.3.1.8 of the pci express base specification (revision 1.1) . v tx-dc-cm the tx dc common mode voltage 0- 3.6v the maximum dc common mode voltage under any conditions. see section 4.3.1.8 of the pci express base specification (revision 1.1) . i tx-short tx short circuit current limit -- 90ma the total current the transmitter can provide when shorted to its ground t tx-idle-min minimum time spent in electrical idle 50 - - ui minimum time a transmitter must be in electrical idle. used by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set. t tx-idle-set-to -idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set -- 20ui after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. th is is considered a de-bounce time for the transmitter to meet electrical idle after transitioning from l0. t tx-idle-to-diff -data maximum time to transition to valid tx specifications after leaving an electrical idle condition -- 20ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a de-bounce time for the tx to meet all tx specifications after leaving electrical idle. rl tx-diff differential return loss 10 - - db measured over 50 mhz to 1.25 ghz. see note 4. rl tx-cm common mode return loss 6- - db measured over 50 mhz to 1.25 ghz. see note 4. z tx-diff-dc dc differential tx impedance 80 - 120 ohms tx dc differential mode low impedance. see note 6. table 47: pcie differential transmitter output specification (continued) symbol parameter min. nom. max. units comments 15. electrical characteristic s > ac timing specifications 225 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required note that all figure and section references are to the pci express base specif ication (revision 1.1) . 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance test load as shown in figure 4-25 and measured using the clock recovery function in section 4.3.3.2. (also see the transmitter compliance eye diagram in figure 4-24). 3. a t tx-eye = 0.75 ui provides for a total sum of deterministic and random jitter of t tx-jitter-max = 0.25 ui for the transmitter using clock recovery function specified in section 4.3.3.2. the t tx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half the total tx jitter budget using the clock recovery function specified in section 4.3.3.2. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of ji tter points on either side is approximately equal as opposed th e averaged time value. this parameter is to be met at the target bit error rate. the t tx_eye_median-to-max-jitter is to be met using the compliance pattern at a sample size of 1,000,000 ui. 4. the transmitter input impedance shall result in a differentia l return loss greater than or equal to 10 db with a differenti al test input signal no less than 200mv (peak value, 400 mv differential peak to peak) swing around ground applied to d+ and d- lines and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 ohms to ground for both d+ and d- line (that is, as measured by a ve ctor network analyzer with 50 ohm probes - see figure 4-25). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20-80% at the transmitter package pins into a test load as shown in figure 4-25 for both v tx-d+ and v tx-d- . 6. z tx-diff-dc is the small signal resistance of the transmitter measured at a dc operating point that is equivalent to that established by connecting a 100-ohm resistor from d+ and d- while the tx is driving a static logic one or logic zero. equivalently, this parameter can be derived by measuring the rms voltage of the tx while transmitting a test pattern into two different differential terminations that are near 100 ohms. small signal resistance is measured by forcing a small change in differential voltage and dividing this by the corresponding change in current. l tx-skew lane-to-lane output skew -2.8 - 500 + 2 ui ps static skew between any two transmitter lanes within a single link c tx ac coupling capacitor 75 - 200 nf all transmitters must be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. tcrosslink crosslink random timeout 0- 1ms this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see section 4.2.6.3 of the pci express base specification (revision 1.1) . table 47: pcie differential transmitter output specification (continued) symbol parameter min. nom. max. units comments 15. electrical characteristics > ac timing specifications 226 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 40: transmitter eye voltage and timing diagram 1 1. this diagram is an excerpt from pci express base specification (revision 1.1), revision 1.1 , ?transmitter compliance eye diagrams,? page 225. 15. electrical characteristic s > ac timing specifications 227 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.6.3 pcie differential r eceiver input specifications the following table lists the specification of parameters for the differential output of the pcie lanes. table 48: pcie differential receiver input specifications symbol parameter min. nom. max. units comments ui unit interval 399.88 400 400.12 ps each ui is 400ps +/-300ppm. ui does not account for ssc dictated variations. see note 7. v rx-diffp-p differential peak to peak input voltage 0.175 - 1.200 v v rx-diffp-p = 2*|v rx-d+ - v rx-d- | see note 8. t rx-eye minimum rx eye width 0.4 - - ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 - t rx-eye = 0.6 ui. see notes 8, 9, and 10. t rx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median --0.3ui jitter is defined as the measurement variation of the crossing points (v rx-diff = 0v) in relation to recovered tx ui. to be measured after the clock recovery function in section 4.3.3.2 of the pci express base specification (revision 1.1) . see notes 8and 9. v rx-cm-acp rms ac peak common mode input voltage --150mv v rx-cm-ac = |v rx-d+ + v rx-d- |/2 - v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ + v rx-d- |/2 see note 8. rl rx-diff differential return loss 10 - - db measured over 50 mhz to 1.25 ghz. see note 11. rl rx-cm common mode return loss 6- -db measured over 50 mhz to 1.25 ghz. see note 11. z rx-diff-dc dc differential input impedance 80 - 120 ohms rx dc differential mode impedance. see note 12. z rx-dc dc input impedance 40 50 60 ohms required rx d+ as well as d- dc impedance (50 ohm +/- 20% tolerance). see notes 8 and 12. z rx-high-imp-dc powered down dc input impedance 200k - - ohms required rx d+ as well as d- dc impedance when the receiver terminations do not have power. see note 13. 15. electrical characteristics > ac timing specifications 228 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 7. no test load is necessarily associated with this value. 8. specified at the measurement point and measured using the clock recovery function specified in section 4.3.3.2. the test lo ad in figure 4-25 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 4-26). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered using the clock recovery function specified in section 4.3.3.2 must be used as a reference for the eye diagram. 9. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.64. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitte r points on either side is approximately equal as opposed the averaged time value. the rx ui recovered using the clock recovery function specified in section 4.3.3.2 must be used as the reference for the eye diagram. this parameter is measured with the equivalent of a zero jitter reference clock. the t rx-eye measurement is to be met at the target bit error rate. the t rx-eye-median-to-max-jitter specification is to be met using the compliance pattern at a sample size of 1,000,000 ui. 10. for more information on the rx-eye measurement, see the pci express jitter and ber white paper. 11. the receiver input impedance shall result in a differential return loss greater than or equal to 10 db with a differential test input signal of no less than 200 mv (peak value, 400mv differential peak to peak) swing around ground applied to d+ and d- lines and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for the return loss measurements is 50 ohms to ground for both d+ and d- lines (that is, as measured by a vector network analyzer with 50-ohm probes - see figure 4-25). note that the series capacitors c tx is optional for the return loss measurement. 12. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5ms transition time before the receiver termination values must be met on all un-configured lanes of a port. 13. the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. this term must be measured at 200mv above the rx ground. v rx-idle-det-diffp electrical idle detect threshold 65 - 175 mv v rx-idle-det-diffp = 2*|v rx-d+ - v rx-d- | measured at the package pins of the receiver. t rx-idle-det-diff-e ntertime unexpected electrical idle enter detect threshold integration time --10ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be longer than t rx-idle-det-entertime to signal an unexpected idle condition. l rx-skew total skew - - 20 ns skew across all lanes on a link. this includes variation in the length of a skp ordered set (for example, com and one to five skp symbols) at the rx as well as any delay differences arising from the interconnect itself. table 48: pcie differential receiver input specifications (continued) symbol parameter min. nom. max. units comments 15. electrical characteristic s > ac timing specifications 229 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 41: minimum receiver eye timing and voltage compliance specification 1 1. this diagram is an excerpt from pci express base specification, revision 1.1 , ?differential receiver (rx) input specifications,? page 230. 15. electrical characteristics > ac timing specifications 230 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.6.4 reference clock the following table lists the peb383 ?s electrical characteristics for the differential serdes reference clock input (pcie_refclk_n/p). figure 42: weighing function for rms phase jitter calculation table 49: reference clock (pcie_refc lk_n/p) electrical characteristics symbol parameter min. typ. max. unit notes v diff differential input voltage 350 710 850 mv - v cm differential input common mode range [(pcie_refclk_p +pcie_refclk_n)/2] 175 - 2000 mv - fin input clock frequency - 100 - mhz - f pcie_refclk_p/n reference clock frequency tolerance -300 - +300 ppm ppm with respect to 100 mhz, based on the pcie specification. fin_dc reference clock duty cycle 40 50 60 % - j clk-ref total phase jitter (rms) - - 3 ps rms see a . a. total permissible phase jitter on the reference clock is 3 ps rms. this value is specified with assumption that the measurement is performed with a 20 gsamples/s scope with more than 1 million samples. the zero-crossing times of each rising edges are recorded and an average reference clock is ca lculated. this average period may be subtracted from each sequential, instantaneous period to find the difference between each reference clock rising edge and the ideal placement to produce the phase jitter sequence. the psd of the phase jitter is calculated and integrated after being weighted with the transfer function shown in figure 42 . the square root of the resulting integral is the rms total phase jitter. zin input impedance - - - - pcie_refclk_p/n is a high-impedance input. magnitude 0 db 20 db/decade 40 db/decade 1.5 mhz 10 mhz frequency 15. electrical characteristic s > ac timing specifications 231 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.6.5 boundary scan test signal timing the following table lists the test signal timings for the peb383. 15.6.6 reset timing the following table lists the reset signal timings for the peb383. table 50: boundary scan test signal timings symbol parameter min max units notes t bsf jt_tck frequency 0 10 mhz - t bsch jt_tck high time 50 - ns measured at 1.5v, a a. not tested. t bscl jt_tck low time 50 - ns measured at 1.5v, a t bscr jt_tck rise time - 25 ns 0.8v to 2.0v, a t bscf jt_tck fall time - 25 ns 2.0v to 0.8v, a t sis1 input setup to jt_tck 10 - ns b b. see figure 43 . t bsih1 input hold from jt_tck 10 - ns b t bsov1 jt_tdo output valid delay from falling edge of jt_tck. -15ns c , d c. outputs precharged to v dd33 . d. see figure 44 . t of1 jt_tdo output float delay from falling edge of jt_tck -15ns c , e e. a float condition occurs when the output current becomes less than i lo . float delay is not tested (see figure 44 ). table 51: reset timing symbol parameter min max units notes t por power supplies in recommended operating range to de-assertion of device reset 100 - ms the pcie specification requires reset (pcie_perstn) to remain asserted for 100 ms after power supplies are valid. t active reset active time 1 -ms - 15. electrical characteristics > ac timing waveforms 232 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 15.7 ac timing waveforms this section contains ac ti ming waveforms for the peb383. figure 43: input timing measurement waveforms - pci_clk clock stable to de-assertion of device reset 100 -us - - power-up strapping hold from de-assertion of device reset 0-ns - t hiz assertion of reset to outputs tri-state - 10 ns - table 51: reset timing (continued) symbol parameter min max units notes clk input valid v test v test v test t is t ih v tl v th v th v tl v max 15. electrical characteristics > ac timing waveforms 233 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 44: output timing measurement waveforms figure 45: pci t ov (max) rising edge ac test load figure 46: pci t ov (max) falling edge ac test load v test clk output float vtrise output delay rise output delay fall v tfall t ov t ov t of v tl v th output te s t point 10pf 25 output 10pf 25 v cc33 te s t point 15. electrical characteristics > ac timing waveforms 234 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required figure 47: pci t ov (min) ac test load output te s t point 10pf 1k 1k v cc33 235 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16. packaging topics discussed include the following: ? ?pinouts and mechanical diagrams? ? ?thermal characteristics? ? ?moisture sensitivity? 16. packaging > pinouts and mechanical diagrams 236 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.1 pinouts and mechanical diagrams 16.1.1 qfp package pinout 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 vdd_pcie vdda_pcie pcie_txd_n pcie_txd_p vss_pcie pcie_rxd_p pcie_rxd_n vss_pcie pcie_rext vss_pcie pcie_refclk_n pcie_refclk_p vdda_pcie vdd_pcie vssa_pll vdda_pll pcie_perstn pwrup_pll_bypass test_on test_bce sr_csn vdd_pci sr_clk sr_dout sr_din pci_clko[0] vss pci_clko[1] vdd pci_clko[2] vss_io pci_clko[3] 1 v ss _ io pci intdn 96 2 pci _ ad [ 0 ] pci _ clko [ 4 ] 95 3 pci _ ad [ 2 ] pci _ intcn 94 4 pci _ ad [ 1 ] pci _ intbn 93 5 pci _ ad [ 3 ] v dd _ pci 92 6 pci ad [ 4 ] pci intan 91 7 v dd _ pci pci _ pmen 90 8 v dd jtag _ tdi 89 9 v ss v ss 88 10 pci ad [ 5 ] v dd 87 11 pci _ ad [ 6 ] jtag _ tdo 86 12 pci _ ad [ 7 ] jtag _ tms 85 13 pci _ cben [ 0 ] jtag _ trstn 84 14 pci ad [ 8 ] jtag tck 83 15 v ss io pci rstn 82 16 pci _ ad [ 9 ] pci _ clk 81 17 pci _ ad [ 10 ] pci _ gntn [ 3 ] 80 18 pci _ ad [ 11 ] v ss _ io 79 19 pci ad [ 12 ] v dd _ pci 78 20 pci _ ad [ 13 ] pci _ gntn [ 2 ] 77 21 vio _ pci pci _ gntn [ 1 ] 76 22 v ss pci _ gntn [ 0 ] 75 23 v dd _ pci pci reqn [ 3 ] 74 24 pci _ ad [ 14 ] v ss 73 25 pci _ ad [ 15 ] vio _ pci 72 26 pci _ cben [ 1 ] v ss _ io 71 27 pci par pci reqn [ 1 ] 70 28 v dd pci reqn [ 2 ] 69 29 v ss pci _ ad [ 31 ] 68 30 pci _ perrn pci _ reqn [ 0 ] 67 31 pci _ serrn v dd _ pci 66 32 pci lockn pci ad [ 30 ] 65 vdd_pci pci_stopn pci_trdyn pci_devseln pci_irdyn pci_framen vss_io vdd vss pci_cben[2] pci_m66en pci_ad[16] pci_ad[17] pci_ad[18] vdd_pci vdd vio_pci pci_ad[19] pci_ad[20] pci_ad[21] pci_ad[22] pci_ad[23] vss_io pci_cben[3] pci_ad[24] pci_ad[25] pci_ad[26] pci_ad[27] vdd vss pci_ad[28] pci_ad[29] 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 top ? view 16. packaging > pinouts and mechanical diagrams 237 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.1.2 qfp package drawing 16. packaging > pinouts and mechanical diagrams 238 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.1.2.1 qfp package drawing ? page 2 16. packaging > pinouts and mechanical diagrams 239 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.1.3 qfn package pinout 16. packaging > pinouts and mechanical diagrams 240 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.1.4 qfn package drawing 16. packaging > pinouts and mechanical diagrams 241 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.1.4.1 qfn package drawing ? page 2 16. packaging > thermal characteristics 242 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 16.2 thermal characteristics heat generated by the packaged silicon must be removed from the package to ensure the silicon is maintained within its functional and maximum de sign temperature limits. if heat buildup becomes excessive, the silicon temperature ma y exceed the temperatur e limits. a consequence of this is that the silicon may fail to meet the performance specificati ons and the reliability objectives may be affected. failure mechanisms and failure rate of a device ha s an exponential dependen ce on the silicon operating temperatures. therefore, the cont rol of the package, and by extension the junction temperature, is essential to ensure product reliability. the peb383 is specified safe for operation when the junction temperature is within the reco mmended limits as shown in table 42 . table 52: thermal specifications ? 66mhz power estimates are based on simulations ? 0.894 w @ 66mhz package parameter air flow unit 0 m/s 1 m/s 2 m/s qfp ? em128 ja 43.9 36.9 33.7 c/w t j max @ t amb =85c 124 118 115 c t j max @ t amb =70c 109 103 100 c jc 14 ? ? c/w qfn ? nq132 ja 23.4 18.5 17 c/w t j max @ t amb =85c 106 102 100 c t j max @ t amb =70c918785 c jc 11.5 c/w jb 0.42 c/w 16. packaging > thermal characteristics 243 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required table 52 and table 53 show the simulated thermal characterist ics (theta ja, theta jb, and theta jc) of the peb383 package at 66mhz and 33mhz respectively. the thermal resistance ja characteristics of a package depends of multiple variables other than just the package. in a typical application, designers must take into account various system-l evel and environmental ch aracteristics, such as: ? package mounting (vertical/horizontal) ? system airflow conditions (laminar/turbulent) ? heat sink design and thermal characteristics ? heat sink attachment method ? pwb size, layer count, and conductor thickness ? influence of the heat dissipating componen ts assembled on the pwb (neighboring effects) the results in table 53 and table 52 are based on a jedec thermal test board configuration (jesd51-9), and does not factor in the system-level characteristics described above. as such, these values are for reference only. table 53: thermal specifications ? 33mhz power estimates are based on simulations ? 0.511 w @ 33mhz package parameter air flow unit 0 m/s 1 m/s 2 m/s qfp ? em128 ja 43.9 36.9 33.7 c/w t j max @ t amb =85c 107 104 102 c t j max @ t amb =70c928987 c jc 14 ? ? c/w qfn ? nq132 ja 23.4 18.5 17 c/w t j max @ t amb =85c979494 c t j max @ t amb =70c827979 c jc 11.5 c/w jb 0.42 c/w 16. packaging > moisture sensitivity 244 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required example of thermal data usage based on above ja data and specified conditions, the junc tion temperature of the peb383 with a 0 m/s airflow can be determined using the following formula: t j = ja * p + t amb where: ?t j is the junction temperature ? p is the power consumption ?t amb is the ambient temperature 16.3 moisture sensitivity the moisture sensitivity level (msl) for the peb383 is 3. 245 peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 17. ordering information valid combinations 89HPEB383zanq 89HPEB383zanq8 132-ballqfn package, commercial temp. 89HPEB383zbnq 89HPEB383zbnq8 132-ballqfn package, commercial temp. 89HPEB383zanqg 89HPEB383zanqg8 132-ball green qfn package, commercial temp. 89HPEB383zbnqg 89HPEB383zbnqg8 132-ball green qfn package, commercial temp. 89HPEB383zaem 89HPEB383zaem8 128-ball tqfp package,commercial temp. 89HPEB383zbem 89HPEB383zbem8 128-ball tqfp package,commercial temp. 89HPEB383zaemg 89HPEB383zaemg8 128-ball green tqfp package, commercial temp. 89HPEB383zbemg 89HPEB383zbemg8 128-ball green tqfp package, commercial temp. nn a aa a operating voltage device temp h product family 89 serial switching product peb pcie bridge 1.0v +/- 0.1v core voltage legend a = alpha character n = numeric character aaa protocol blank commercial temperature (0c to +70c ambient) za revision za n tape & range reel 8 tape & reel nq 132 132-ball qfn aaa pkg 383 product number a product 132 132-ball qfn, green nqg revision detail em 128 128-ball tqfp 128 128-ball tqfp, green emg zb revision zb peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required 17. ordering information > 246 i peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required glossary address decode window the address range defined by a device?s base a ddress registers when operating in non-transparent addressing mode. if a transaction a ddress on the bus falls within a device?s address decode window, the device claims the transaction. base and limit register a configuration register that stores memory or i/o address decode information in a device. if the address of a transaction falls within the window de fined by a device?s base and limit registers, the device claims the transaction. base and limit registers are used only by transparent bridges. compact pci cpci. it is an adaptation of the pci local bus specification (revision 2.2) for industrial and/or embedded applications that requi re a more robust mechanical fo rm factor than desktop pci. completer (pcie) the device that is targeted by a requester during a pcie transacti on. a requester reads data from a completer, or writes data to a completer. a requester can be eith er a root complex or an endpoint device. completer id this value uniquely identifies the completer of a tran saction request. it consists of a completer?s bus number, device number, and function number. configuration transaction a read or write access of a pci device?s configur ation registers. downstream port a pcie port that points in the direction away from the root complex (for example, a root complex port). egress port a pcie port that transmits a packet to another pcie device. endpoint a type of pcie device, or mode of operation, that function as re questers or completers of pcie transactions (examples include ethe rnet, usb, and graphic devices). if a pcie port is not configured as a root complex or a switch then it is consider ed an endpoint. an endpoint can support up to eight functions. fairness algorithm arbitration logic that helps low and high priority device s gain fair access to a peripheral bus. this logic also helps prevent deadlocks among bus-mastering devi ces in a system. flow control the method of communicating receive buffer status from a receiver to a transmitter to prevent receive buffer overflow and to allow transmitter compliance with ordering rules. hierarchy a pcie fabric of all devices and links associated with a root comp lex. the devices can be connected either directly or indirect ly (through switches and bridges) to the root complex. hot swap this refers to the process of inserting and extracting compactpci boards from an active system without adversely affect ing system operation. ingress port a pcie port that receives a pa cket from another pcie device. link an interconnection between two pcie devices. a link cons ists of either x1, x2, x4, x8, x16, or x32 pairs of signals between two devices. each grouping of si gnals is referred to as a lane . memory-mapped i/o mio. memory-mapped i/o is used for non-prefetchable pci memory transactions. glossary ii peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required message a tlp used to communicate info rmation outside of the memory, i/o, and confi guration spaces. message tlps are always posted, a nd may or may not contain data. non-transparent addressing this type of addressing is used by a pci bridging device to isolate the primary address map from the secondary address map. it provide s address translation for pci devi ces located in separate address domains with multiple host proces sors. this mode of operation, wh ich is sometimes called embedded bridging, allows for distinct pci memory spac es to be connected through defined windows with address translation from one me mory domain to another. pci extended capabilities optional features supported by the pci local bus specification . some examples of extended capabilities include : vital product data, message signaled interrupts, and sl ot numbering. a device that supports extended capabilities uses a pci capability list to acce ss the features located in its pci configuration space. prefetchable memory the process of prefetching memory occurs when a line of information from memory is read before a bus master requests it. if a bus master later requests the memory lin e, the bus target can supply it immediately. this type of memory access minimizes the time required to retrieve target memory. requester (pcie) the device that originates a pcie transaction. a re quester can be either a ro ot complex or an endpoint device. requester id (pcie) this value uniquely identifies the requester of a tran saction. it cons ists of a request er?s bus number, device number, and function number. root complex this is a type of pcie device, or mode of opera tion, that connects a host processor and memory sub-system to a pcie fabric. the root complex ge nerates transaction request s on behalf of the host processor ? such as configuration, memory, and i/o ? to other devices in the pcie hierarchy. it also handles interrupts and power management events. the root complex appears as p2p bridge(s) to the pc ie links, and can support one or more pcie ports. transparent addressing this type of pci addressing is used by a bri dging device to support conf iguration mapping but not perform address transl ation between two buses. when a device is configured in transparent mode, it provides standard pci bus bridging support through its base and limit registers. th ese registers define address decode windows for multiple bridges so that transactions ca n be passed transparently in a system. this enables devices that are connected to mu ltiple bridging devices to share a single, unified address space. upstream port a pcie port that points in the direction of th e root complex (for example, an endpoint port). peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required iii index a absolute maximum ratings 219 ac timing pci interface 222 ac timing specifications 222 ac timing waveforms 232 address decoding i/o memory 32 isa 35 memory-mapped i/o 29 non-transparent 37 prefetchable memory 31 vga 34 advanced error reporting capability registers 188 arbitration 59 aspm 94 b buffer downstream non-posted 26 downstream posted 26 upstream non-posted 24 upstream posted 25 buffer management 50 bus arbiter 59 c clocking pci 91 pcie 90 cold reset 88 completer abort completion status errors 79 configuration retry 47 configuration transaction overview 43 type 0 44 type 1 44 type 1 to special cycle 46 type 1 to type 0 45 type 1 to type 1 45 d d state transitions 98 d0 state 97 d3cold state 97 d3hot state 97 dc and operating characteristics 221 device power states 97 device register map 120 document conventions document status 2 numeric conventions 2 symbols 2 downstream data path 22 non-transparent registers 184 e ecrc error 70 eeprom controller 101 eeprom device 102 eeprom image 104 error handling 65 pci 75 pcie 68 exclusive access 57 f flow control advertisements 49 credits 27 overview 26 h hot reset 89 i i/o addressing 32 ieee 1149.1 interface 111 interrupt handling 63 interrupt routing 64 interrupt sources 64 isa addressing 35 j jtag 109 read access 112 write access 111 jtag test pins 113 jtag_tck signal 19 jtag_tdi signal 19 jtag_tdo signal 19 jtag_tms signal 19 jtag_trstn signal 19 l l0 state 95 l1 state 95 l2/l3 ready 95 l3 state 95 ldn state 95 los state 95 m master-abort errors 73 index iv peb383 user manual july 25, 2011 integrated device technology, inc. confidential - nda required mechanical diagram 236 memory-mapped i/o addressing 29 message signaled interrupts (msi) 63 message signaled interrupts (msi-x) 63 message transactions 55 message-based interrupts enhanced message signaled interrupts 63 message signaled interrupts 63 n non-transparent addressing 37 non-transparent registers downstream 184 upstream 156 o ordering information 245 p pci capabilit y registers 159 pci clocking 91 pci errors 76 pci interface ac timing 222 pci reset 89 pci transactions 53 pcie capability registers 173 pcie clocking 90 pcie configuration space 117 pcie enhanced configuration 46 pcie link states 96 pcie reset 88 pcie transactions 54 poisoned tlp 69 power characteristics 220 power management 93 power management event 98 power states 94 power supply sequencing 221 prefetchable memory addressing 31 prefetching algorithm 27 r recommended operating conditions 220 register map 120 requestor id 50 reset pci 89 pcie 88 round-robin arbitration 60 s serdes tap controller 113 short term caching 28 system errors 80 t tap controller 110 target-abort errors 74 tck signal 19 tdi signal 19 tdo signal 19 thermal characteristics 242 timeout errors 79 timing waveforms 232 tms signal 19 transaction forwarding pci to pcie 51 pcie to pci 50 transaction management downstream 24 upstream 23 transaction ordering 56 transactions supported pci 53 pcie 54 trstn signal 19 type 0 configurat ion transaction 44 type 1 configurat ion transaction 44 type 1 to special cycle configuration transaction 46 type 1 to type 0 conf iguration transaction 45 type 1 to type 1 conf iguration transaction 45 typical applications 10 u uncorrectable address/attribute errors 72 uncorrectable data error 71 undefined 116 unsupported request completion status errors 79 upstream data path 21 non-transparent registers 156 v vga addressing 34 w warm reset 88 |
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